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An automatic hierarchical delay analysis tool

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Abstract

The performance analysis of VLSI integrated circuits (ICs) with flat tools is slow and even sometimes impossible to complete. Some hierarchical tools have been developed to speed up the analysis of these large ICs. However, these hierarchical tools suffer from a poor interaction with the CAD database and poorly automatized operations. We introduce a general hierarchical framework for performance analysis to solve these problems. The circuit analysis is automatic under the proposed framework. Information that has been automatically abstracted in the hierarchy is kept in database properties along with the topological information. A limited software implementation of the framework, PREDICT, has also been developed to analyze the delay performance. Experimental results show that hierarchical analysis CPU time and memory requirements are low if heuristics are used during the abstraction process.

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Authors and Affiliations

  1. École Polytechnique de Montréal, Succ. “A”, C.P. 6079, H3C 3A7, Montréal, Québec, Canada

    Farid Mheir-El-Saadi & Bozena Kaminska

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  1. Farid Mheir-El-Saadi
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  2. Bozena Kaminska
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This work is supported by grants from the Natural Sciences and Engineering Research Council (Canada) (NSERC) and the Ministry of Higher Education (Québec).

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Mheir-El-Saadi, F., Kaminska, B. An automatic hierarchical delay analysis tool. J. of Comput. Sci. & Technol. 9, 349–364 (1994). https://doi.org/10.1007/BF02943582

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  • DOI: https://doi.org/10.1007/BF02943582

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