Skip to main content
Log in

A framework of memory consistency models

  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

Previous descriptions of memory consistency models in shared-memory multiprocessor systems are mainly expressed as constraints on the memory access event ordering and hence are hardware-centric. This paper presents a framework of memory consistency models which describes the memory consistency model on the behavior level. Based on the understanding that the behavior of an execution is determined by the execution order of conflicting accesses, a memory consistency model is defined as an interprocessor synchronization mechanism which orders the execution of operations from different processors. Synchronization order of an execution under certain consistency model is also defined. The synchronization order, together with the program order, determines the behavior of an execution.

This paper also presents criteria for correct program and correct implementation of consistency models. Regarding an implementation of a consistency model as certain memory event ordering constraints, this paper provides a method to prove the correctness of consistency model implementations, and the correctness of the lock-based cache coherence protocol is proved with this method.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Lamport L. How to make a multiprocessor computer that correctly executes multiprocessor programs.IEEE Transactions on Computers, 1979, C-28(9): 690–691.

    Article  MATH  Google Scholar 

  2. Adve S, Hili M. Weak ordering: A new definition. InProceedings of the 17th Annual International Symposium on Computer Architecture, pp. 1–14, June 1990.

  3. Adve S. Designing memory consistency models for shared-memory multiprocessors.Computer Sciences Technical report #1198, University of Wisconsin-madison, Dec. 1993.

  4. Adve S, Gharachorloo K. Shared memory consistency models: a tutorial.IEEE Computer, pp. 66–76. December 1996.

  5. Hu Weiwu, Shi Weisong, Tang Zhimin. A lock-based cache coherence protocol for scope consistency.Journal of Computer Science and Technology, 1998, 13(2): 97–109.

    Article  Google Scholar 

  6. Scheurich C, Dubois M. Correct memory operation of cached-based multiprocessors. InProceedings of the 14th Annual International Symposium on Computer Architecture, pp. 234–243, May 1987.

  7. Gharachorloo K, Lenoski D, Laudon J, Gibbons P, Gupta A, Hennessy J. Memory consistency and event ordering in scalable shared-memory multiprocessors. InProceedings of the 17th Annual International Symposium on Computer Architecture, pp. 15–26, June 1990.

  8. Goodman J. Cache consistency and sequential consistency.Technical Report No. 61, SCI Committee, March 1989.

  9. Dubios M, Scheurich C, Briggs F. Memory access buffering in multiprocessors. InProceedings of the 13th International Symposium on Computer Architecture, pp. 434–442, June 1986.

  10. Carter J B, Bennet J K, Zwaenepoel W. Implementation and performance of munin. InProc. of the 13th ACM Symp. on Operating Systems Principles (SOSP’91), pp. 152–164, October 1991.

  11. Amza C, Dwarkadas S, Keleher P, Cox A, Zwaenepoel W. TreadMarks: Shared memory computing on networks of workstations.IEEE Computer, 1996, 29(2):18–28.

    Google Scholar 

  12. Iftode L, Singh J, Li K. Scope consistency: A bridge between release consistency and entry consistency. InProceedings of the 8th Annual ACM Symposium on Parallel Algorithms and Architectures, June 1996.

  13. Bershad B N, Zekauskas M J, Sawdon W A. The midway distributed shared memory system. InProc. of the 38th IEEE Int’l Computer Conf. (COMPCON Spring’93), pp. 528–537, February 1993.

  14. Shasha D, Snir M. Efficient and correct execution of parallel programs that share memory.ACM Transactions on Programming Languages and System, 1988, 10(2): 282–312.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Hu Weiwu.

Additional information

The work of this paper is supported by the Climbing Program, the National Natural Science Foundation of China, and the President Young Creation Foundation of the Chinese Academy of Sciences.

For the biography ofHu Weiwu please refer to p.109, No.2, Vol.13 of this Journal.

For the biography ofShi Weisong please refer to p.109, No.2, Vol.13 of this Journal.

For the biography ofTang Zhimin please refer to p.109, No.2, Vol.13 of this Journal.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hu, W., Shi, W. & Tang, Z. A framework of memory consistency models. J. of Comput. Sci. & Technol. 13, 110–124 (1998). https://doi.org/10.1007/BF02946600

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF02946600

Keywords

Navigation