Abstract
Previous descriptions of memory consistency models in shared-memory multiprocessor systems are mainly expressed as constraints on the memory access event ordering and hence are hardware-centric. This paper presents a framework of memory consistency models which describes the memory consistency model on the behavior level. Based on the understanding that the behavior of an execution is determined by the execution order of conflicting accesses, a memory consistency model is defined as an interprocessor synchronization mechanism which orders the execution of operations from different processors. Synchronization order of an execution under certain consistency model is also defined. The synchronization order, together with the program order, determines the behavior of an execution.
This paper also presents criteria for correct program and correct implementation of consistency models. Regarding an implementation of a consistency model as certain memory event ordering constraints, this paper provides a method to prove the correctness of consistency model implementations, and the correctness of the lock-based cache coherence protocol is proved with this method.
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The work of this paper is supported by the Climbing Program, the National Natural Science Foundation of China, and the President Young Creation Foundation of the Chinese Academy of Sciences.
For the biography ofHu Weiwu please refer to p.109, No.2, Vol.13 of this Journal.
For the biography ofShi Weisong please refer to p.109, No.2, Vol.13 of this Journal.
For the biography ofTang Zhimin please refer to p.109, No.2, Vol.13 of this Journal.
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Hu, W., Shi, W. & Tang, Z. A framework of memory consistency models. J. of Comput. Sci. & Technol. 13, 110–124 (1998). https://doi.org/10.1007/BF02946600
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DOI: https://doi.org/10.1007/BF02946600