Skip to main content
SpringerLink
Log in

Out-of-order execution in sequentially consistent shared-memory systems: Theory and experiments

  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

Traditional implementation of sequential consistency in shared-memory systems requires memory accesses to be globally performed in program order. Based on an event ordering model for correct executions in shared-memory systems, this paper proposes and proves that out-of-order execution does not influence the correctness of an execution providing certain condition is met. Simulation results show that out-of-order execution proposed in this paper is an effective way to improve the performance of a sequentially consistent shared-memory system.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Lamport L. How to make a multiprocessor computer that correctly executes multiprocessor programs.IEEE Transactions on Computers, 1979, C-28(9): 690–691.

    Article  MATH  Google Scholar 

  2. Gharachorloo K, Lenoski D, Laudon Jet al. Memory consistency and event ordering in scalable shared-memory multiprocessors. InProceedings of the 17th Annual International Symposium on Computer Architecture, 1990, pp.15–26.

  3. Shasha D, Snir M. Efficient and correct execution of parallel programs that share memory.ACM Transactions on Programming Languages and System, 1988, 10(2): 282–312.

    Article  Google Scholar 

  4. Scheurich C, Dubois M. Correct memory operation of cached-based multiprocessors. InProceedings of the 14th Annual International Symposium on Computer Architecture, 1987, pp.234–243.

  5. Coller W. Reasoning About Parallel Architectures. Englewood Cliffs (ed.), NJ: Prentice-Hall, 1992.

    Google Scholar 

  6. Archibald J, Baer J. Cache coherence protocols: evaluation using a multiprocessor simulation model.ACM Transactions on Computer Systems, 1986, 4: 273–298.

    Article  Google Scholar 

  7. Tomasevic M, Milutinovic V. A simulation study of snoopy cache coherence protocols. InProceedings of the 25th Hawaii International Conference on System Sciences, 1992, pp.427–436.

  8. Dubios M, Briggs F. Effects of csche coherence in multiprocessors.IEEE Transaction on Computers, 1982, C-31(11): 1083–1099.

    Article  Google Scholar 

  9. Dubios M, Scheurich C, Briggs F. Memory access buffering in multiprocessors. InProceedings of the 13th International Symposium on Computer Architecture, 1986, pp.434–442.

  10. Dubios M, Scheurich C, Briggs F. Synchronization, coherence, and event ordering in multiprocessors.Computer, 1988, 21(2): 9–21.

    Article  Google Scholar 

  11. Adve S, Hill M. Weak Ordering: A new definition. InProceedings of the 17th Annual International Symposium on Computer Architecture, 1990, pp.1–14.

  12. Goodman J. Cache Consistency and sequential consistency.Technical Report No. 61, SCI Committee, March 1989.

  13. Gharachorloo K, Gupta A, Hennessy J. Two techniques to enhance the performance of memory consistency models. InProceedings of the 1991 International Conference on Parallel Processing, 1991, pp.I-335-I-364.

  14. Herbert B. Enderton. Elements of Set Theory. London: Academic Press, Inc. Ltd., 1977.

    Google Scholar 

  15. Lenoski D, Laudon J, Gharachorloo Get al. The directory-based cache coherence protocol for the DASH multiprocessors. InProceedings of the 17th Annual International Symposium on Computer Architecture, 1990, pp.148–158.

Download references

Author information

Authors and Affiliations

  1. Institute of Computing Technology, Chinese Academy of Sciences, 100080, Beijing, P.R. China

    Hu Weiwu & Xia Peisu

Authors
  1. Hu Weiwu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Xia Peisu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Hu Weiwu.

Additional information

The work is supported by the President Young Investigator Foundation of Chinese Academy of Sciences and the National Natural Science Foundation of China.

For the biography ofHu Weiwu please refer to p.109, No.2, Vol.13 of this Journal.

Xia Peisu in an Academician of the Chinese Academy of Sciences and a Professor of the Institute of Computing Technology. She received her Ph.D. degree in electrical engineering from University of Edinburgh, United Kindom, in 1950. Her current research interests include computer architecture, computer engineering, high speed pipeline system and parallel processing.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hu, W., Xia, P. Out-of-order execution in sequentially consistent shared-memory systems: Theory and experiments. J. of Comput. Sci. & Technol. 13, 125–140 (1998). https://doi.org/10.1007/BF02946601

Download citation

  • Received:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF02946601

Keywords

Search

Navigation