Abstract
The paper proposes a novel ATPG (Automatic Test Pattern Generation) method based on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware Description Language). The method is simulation-based. Firstly, it abstracts RTL behavioral descriptions to Process Controlling Trees (PCT) and Data Dependency Graphs (DDG), which are used for behavioral simulation and data tracing. Transfer faults are extracted from DDG edges, which compose a fault set needed for test generation. Then, simulation begins without specifying inputs in advance, and a request-echo strategy is used to fix some uncertain inputs if necessary. Finally, when the simulation ends, the partially fixed input sequence is the generated test sequence. The proposed request-echo strategy greatly reduces unnecessary backtracking, and always tries to cover uncovered transfer faults. Therefore, the proposed method is very efficient, and generates tests with good quality. Experimental results demonstrate that the proposed method is better than ARTIST in three aspects: (1) the CPU time is shorter by three orders of magnitude; (2) the test length, is shorter by 52%; and (3) the fault coverage is higher by 0.89%.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Min, Y, Su S Y H. Testing functional faults in VLSL. InProc. ACM/IEEE 19th Design Automation Conf., Las Vegas, NA, USA, June, 1982, pp.384–392.
Corno F, Reorda M Sonza, Squillero G. High-level observability for effective high-level ATPG. InProc. 18th IEEE VLSI Test Symposium (VTS2000), Montreal, Canada, May, 2000, pp.411–416.
Corno F, Reorda M Sonza, Squillero G. RTL ITC99 benchmarks and first ATPG result.IEEE Design & Test of Computers, July–August 2000, pp.44–53.
Corno F, Prinetto P, Rebaudengo Met al. GATTO: A genetic algorithm for automatic test pattern generation for large synchronous circuits.IEEE Trans. Computer-Aided Design, August, 1996, 15(8): 943–951.
Chiusano S, Corno F, Prinetto P. A test pattern generation algorithm exploiting behavioral information. InProc. IEEE Asian Test Symposium (ATS'98), Singapore, December, 1998, pp.480–485.
Tupuri R S, Krishnamachary A, Abraham J A. Test generation for gigahertz processors using an automatic functional constraint extractor. InProc. ACM/IEEE Design Automation Conference (DAC'99), 1999, New Orleans, Louisiana, pp.647–652.
Chen C H, Noh T H. VHDL behavioral ATPG and fault simulation of digital systems.IEEE Trans. Acrospace and Electronic System, April, 1998, 34(2): 428–447.
Indradeep Ghosh, Masahiro Fujita. Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, March, 2001, 20(3): 402–415.
Author information
Authors and Affiliations
Corresponding author
Additional information
This work is supported by the National Natural Science Foundation of China under Grant Nos.69733010,90207002 and 60242001, and also by the Youth Science Foundation of Institute of Computing Technology under Grant No.20016280-18.
The main part of the paper was presented at the 10th IEEE Asian Test' Symposium, Kyoto, Japan, Nov. 2001, and honored with the Teruhiko Yamata Memorial Award.
YIN ZhiGang received his B.S. degree in computer science from China University of Geosciences in 1998, and then entered Institute of Computing Technology, Chinese Academy of Sciences as a graduate student. He is now a Ph.D. candidate in the same institute. His current research interests include VLSI testing, HDL, and Design Verification.
MIN YingHua graduated from Mathematics Department of Jilin University in 1962. He has visited Stanford and other universities in the US for years since 1981, and served on numerous program committees of IEEE international conferences. He is a fellow of IEEE, a member of ACM, and a professor at Institute of Computing Technology, Chinese Academy of Sciences, and Hunan University. His current research interests include electronic testing, dependable computing, software reliability, and networking modeling.
LI XiaoWei received his Ph.D. degree in compute science from Institute of Computing Technology, Chinese Academy of Sciences in 1991. He had worked as an associated professor in Peking University since 1993. He is now a professor at Institute of Computing Technology, Chinese Academy of Scineces. His current research interests include SOC/VLSI test and DFT, microprocessor test and verification, low power design and test, software test and software reliability.
LI HuaWei received her B.S. degree in computer science from Xiangtan University in 1996, and M.S. and Ph.D. degrees from Institute of Computing Technology, Chinese Academy of Sciences in 1999 and 2001 respectively. She is now an associated professor at Institute of Computing Technology, Chinese Academy of Sciences. Her current research interests include electronic testing and fault-tolerant computing
Rights and permissions
About this article
Cite this article
Yin, Z., Min, Y., Li, X. et al. A novel RTL behavioral description based ATPG method. J. Comput. Sci. & Technol. 18, 308–317 (2003). https://doi.org/10.1007/BF02948900
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF02948900