Abstract
Accurate simulations of parallel programs for large datasets can often be slow; parallel execution has been shown to offer significant potential in reducing the execution time of many discrete-event simulators. In this paper, we describe the design and implementation of a parallel simulator called DPSIM that simulates the execution of data parallel programs on contemporary message-passing parallel architectures. The simulator has been implemented on the IBM SPx using a conservative synchronization algorithm. This paper also describes the use of the simulator in evaluating the impact of architectural characteristics like processor speed and message communication latency on the performance of scientific applications including Gauss Jordan elimination and matrix multiplication.
This research was supported in part by an ARPA/CSTO Award (No. F30602-94-C-0273)
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© 1996 Springer-Verlag Berlin Heidelberg
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Prakash, S., Bagrodia, R. (1996). Parallel simulation of data parallel programs. In: Huang, CH., Sadayappan, P., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1995. Lecture Notes in Computer Science, vol 1033. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0014203
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DOI: https://doi.org/10.1007/BFb0014203
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