Abstract
The performance and hardware complexity of super-scalar architectures is hindered by conditional branch instructions. When conditional branches are encountered in a program, the instruction fetch unit must rapidly predict the branch predicate and begin speculatively fetching instructions with no loss of instruction throughput. Speculative execution has a high hardware cost, is limited by dynamic branch prediction accuracies, and does not scale well for increasingly super-scalar architectures.
The conditional branch bottleneck would be solved if we could somehow move branch condition evaluation far forward in the instruction stream and provide a new branch instruction that encoded both the source and target address of a branch. This paper summarizes the hardware extensions to support just such a Future Branch, then gives a compiler algorithm for hoisting branch evaluation across many blocks. The algorithm is applicable to other optimizations for parallelism, such as prefetching data.
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References
Aho, A. V., Sethi, R., and Ullman, J. D.Compilers: Principles, Techniques, and Tools. Addison Wesley Publishing Company, Reading, Massachusetts, 1987.
Appelbe, B., Doddapaneni, S., Harmon, R., May, P., Wills, S., and Vitale, M. Future branches — beyond speculative execution. In Micro-28 ((submitted)).
Duvvuru, S., and Arya, S. Evaluation of a Branch Target Address Cache.
Goodman, J. R., Hseih, J. T., Liou, K., Pleszkun, A. R., Schechter, P., and Young, H. C. ”pipe: A vlsi decoupled architecture”. In Proceedings of The Twelfth Annual Symposium on Computer Architecture (1989), pp. 20–27.
Gupta, R. Generalized dominators and post-dominators. In Principles of Programming Languages (San Francisco, California, 1992), p. 246.
Hennessy, J. L., and Patterson, D. A.Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Inc., San Mateo, California, 1990.
Sector, M. S. P.MC88110 Second Generation RISC Microprocessor Users Manual. Motorola, Inc., Phoenix, Arizona, 1991.
Song, S. P., and Denman, M. The PowerPC 604 Microprocessor. IEEE Micro (October 1994), 8–17.
Thompson, T., and Ryan, B. PowerPC 620 Soars. BYTE (November 1994), 113–120.
Wayner, P. SPARC Strikes Back. BYTE (November 1994), 105–112.
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© 1996 Springer-Verlag Berlin Heidelberg
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Appelbe, B., Doddapaneni, S., Harmon, R., May, P., Wills, S., Vitale, M. (1996). Hoisting branch conditions —improving super-scalar processor performance. In: Huang, CH., Sadayappan, P., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1995. Lecture Notes in Computer Science, vol 1033. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0014207
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DOI: https://doi.org/10.1007/BFb0014207
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