Skip to main content
SpringerLink
Log in
Book cover

International Symposium on Theoretical Aspects of Computer Software

TACS 1997: Theoretical Aspects of Computer Software pp 562–582Cite as

Symbolic model-checking method based on approximations and binary decision diagrams for real-time systems

  • Session 8
  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1281))

Abstract

Real-time systems can be described using the timed automata of Alur and Dill. Although there exist model-checking algorithms for timed automata, the problem is intractable (PSPACE-complete). In this paper, we propose a model-checking method based on approximations and symbolic representations. We recursively refine over- and underapproximations to compute the set of states that satisfy a temporal formula. The approximate sets are represented using a combination of BDDs (Binary Decision Diagrams) and DBMS (Difference Bound Matrices). We have developed a verification tool based on this method. As a case study, we check safety and liveness properties of an Ethernet protocol.

This is a preview of subscription content, log in via an institution.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. R. Alur, D.L. Dill. Automata for modeling real-time systems. In Proc. of 17th ICALP, LNCS 443, pp. 322–335, Springer-Verlag, 1990.

    Google Scholar 

  2. J.R. Burch, E.M. Clarke, K.L. McMillan and D.L. Dill. Sequential Circuit Verification Using Symbolic Model Checking. In Proc. of 27th Design Automation Conference, pp. 46–51, 1990.

    Google Scholar 

  3. R. Alur, C. Courcoubetis, D.L. Dill. Model checking for real-time systems. In Proc. of 5th LICS, pp. 414–425, 1992.

    Google Scholar 

  4. T.A. Henzinger, X. Nicollin, J. Sifakis, and S. Yovine. Symbolic model checking for real-time systems. In Proc. of 7th LICS, pp. 394–406, 1992.

    Google Scholar 

  5. Kim G. Larsen, Paul Pettersson, and Wang Yi. Diagnostic Model-Checking for Real-Time Systems. In LNCS 1066, pp. 575–586, 1996.

    Google Scholar 

  6. H. Wong-Toi and D.L. Dill. Approximations for verifying timing properties. In Theories and Experiences for Real-Time System Development, chapter 7, pp 177–204, World Scientific, 1993.

    Google Scholar 

  7. D.L. Dill and H. Wong-Toi. Verification of real-time systems by successive over and under approximation. In Proceedings of Seventh Conference on Computer-Aided Verification, Liege, Belgium. LNCS 939, pp. 409–422, Springer-Verlag, 1995.

    Google Scholar 

  8. R. E. Bryant. Graph-based algorithms for boolean function manipulation. In IEEE Transactions on Computers. Vol. C-35, No.8, pp. 677–691, IEEE Computer Society, 1986.

    Google Scholar 

  9. D.L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Automatic Verification Methods for Finite State Systems, International Workshop. LNCS 407, pp. 197–211, Springer-Verlag, 1989.

    Google Scholar 

  10. R. Alur, C. Courcoubetis, D. Dill N. Halbwachs and H. Wong-Toi. An implementation of three algorithms for timing verification based on automata emptiness. In Proceedings of IEEE RTSS, pp. 157–166, Phoenix, AZ, 1992.

    Google Scholar 

  11. E.M. Clarke, E. C. Browne E. A. Emerson, and A. P. Sistla. Using temporal logic for automatic verification of finite state systems. In Logics and Models of Concurrent Systems, pp. 3–25, Springer-Verlag, 1985

    Google Scholar 

  12. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel E. Macci, A. Prado, F. Somenzi. Algebraic Decision Diagrams and their application. In Proc. 33th IEEE CAD, pp. 188–191, 1993.

    Google Scholar 

  13. E. M. Clarke, K. L. McMillan, X. Zhao, M. Fujita, J. Yang. Spectral transforms for large boolean functions with applications to technology mapping. In Proc. 30th ACM/IEEE Design Automation Conference, pp. 54–60, 1993.

    Google Scholar 

  14. E. Asarin, M. Bozga, A. Kerbrat, O. Maler, A. Pnueli, A. Rasse. Data structures for the verification of timed automata. In LNCS 1201, pp. 575–586, 1997.

    Google Scholar 

  15. S. Minato, N. Ishiura, S. Yajima. Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation. In Proc. 27th ACM/IEEE Design Automation Conference, pp. 52–57, 1990.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, Faculty of Science, The University of Shimane, 1060 Nishikawatu, 690, Matsue City, Japan

    Satoshi Yamane & Kazuhiro Nakamura

Authors
  1. Satoshi Yamane
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kazuhiro Nakamura
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Martín Abadi Takayasu Ito

Rights and permissions

Reprints and permissions

Copyright information

© 1997 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Yamane, S., Nakamura, K. (1997). Symbolic model-checking method based on approximations and binary decision diagrams for real-time systems. In: Abadi, M., Ito, T. (eds) Theoretical Aspects of Computer Software. TACS 1997. Lecture Notes in Computer Science, vol 1281. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0014568

Download citation

  • DOI: https://doi.org/10.1007/BFb0014568

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63388-4

  • Online ISBN: 978-3-540-69530-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation