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Efficient testing of optimal time adders

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 233))

Abstract

We consider the design of two well-known optimal time adders: the ”carry look-ahead” adder ([BrKu]) and the ”conditional sum” adder ([Sk]).

It is shown, that 6log(n) – 4, resp. 6log(n)+2, test patterns suffice to exhaustively test the n-bit carry look-ahead adder, resp. the n-bit conditional sum adder with respect to the single stuck-at fault model.

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References

  1. M.S. Abadir, H.K. Reghbati: ‘Functional Testing of Semiconductor Random Access Memories', Computing Surveys, Vol.15, 1983, pp175–198

    Google Scholar 

  2. J.A. Abraham, D.D. Gajski: ‘Design of Testable Structures Defined by Simple Loops', IEEE Trans., C-30, 1981, pp875–883

    Google Scholar 

  3. B.Becker: ‘An Easily Testable Optimal-Time VLSI Multiplier', T.R., 3/1985, SFB 124, Saarbrücken 1985

    Google Scholar 

  4. B.Becker: ‘Efficient Testing of Optimal Time Adders', T.R., 4/1985, SFB 124, Saarbrücken 1985

    Google Scholar 

  5. R.P. Brent, H.T. Kung: ‘A Regular Layout for Parallel Adders', IEEE Trans. on Comp., C-31, 1982, pp260–264

    Google Scholar 

  6. M.A. Breuer, Ed.: ‘Diagnosis and Reliable Design of Digital Systems', Woodland Hills, CA: Computer Science Press, 1976

    Google Scholar 

  7. W. Daehn, J. Mucha: ‘A Hardware Approach to Self-Testing of large PLA's', IEEE Trans. CAS-28, p1033, 1981

    Google Scholar 

  8. J.Ferguson, J.P.Shen: ‘The Design of Two Easily-Testable VLSI Array Multipliers', Proc. 6th Symp. on Comp. Arithmetic, June 20–22, 1983, Aarhus, Denmark, IEEE Catalog No. 83CH1892-9

    Google Scholar 

  9. A.D. Friedman: ‘Easily Testable Iterative Systems', IEEE Trans. on Comp., C-22, 1973, pp1061–1064

    Google Scholar 

  10. G.Hotz, B.Becker, R.Kolla, P.Molitor: ‘Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise', Informatik Forschung und Entwicklung, 1, 1986, pp38–47, Springer Verlag

    Google Scholar 

  11. W.H.Kautz: ‘Testing for Faults in Cellular Logic Arrays', Proc. of 8th Symp. on Switch. Autom. Th., 1967, pp161–174

    Google Scholar 

  12. R.K.Montoye, J.A.Abraham: ‘Built-in Tests for Abitrarily Structured VLSI Carry Look-Ahead Adders', IFIP 1983, pp361–371

    Google Scholar 

  13. J. Sklansky: ‘Conditional-sum Addition Logic', IRE-EC 9, 1960, pp226–231

    Google Scholar 

  14. J.E. Smith: ‘Detection of Faults in PLA's', IEEE Trans. on Comp., C-28, p845, 1979

    Google Scholar 

  15. J.Vuillemin, L.Guibas: ‘On Fast Binary Addition in MOS Technologies', ICCC 82, pp147–150

    Google Scholar 

  16. W.K.Luk, J.Vuillemin: ‘Recursive Implementation of Optimal Time VLSI Integer Multipliers, IFIP 1983, pp155–168

    Google Scholar 

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Jozef Gruska Branislav Rovan Juraj Wiedermann

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© 1986 Springer-Verlag Berlin Heidelberg

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Becker, B. (1986). Efficient testing of optimal time adders. In: Gruska, J., Rovan, B., Wiedermann, J. (eds) Mathematical Foundations of Computer Science 1986. MFCS 1986. Lecture Notes in Computer Science, vol 233. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0016245

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  • DOI: https://doi.org/10.1007/BFb0016245

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-16783-9

  • Online ISBN: 978-3-540-39909-4

  • eBook Packages: Springer Book Archive

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