Skip to main content
SpringerLink
Log in
Book cover

International Conference on High-Performance Computing and Networking

HPCN-Europe 1994: High-Performance Computing and Networking pp 105–110Cite as

A distributed automatic test pattern generation system

  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 796))

Abstract

The fault parallel approach to the automatic test pattern generation (ATPG) distributes the target faults to be processed in parallel. Every processor performs the complete test pattern generation and fault simulation for its faults.

In this article we describe our procedures to gain nearly linear speedup on large workstation networks using suitable methods for fault distribution, dynamic load balancing, and fault tolerance. Experimental results validate the efficiency of our approach.

This research is supported by the DFG (Deutsche Forschungsgemeinschaft) within the project SFB 0342 (Tools and Methods for Utilizing Parallel Computers)

This is a preview of subscription content, log in via an institution.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. R. H. Klenke, R. D. Williams, and J. H. Aylor, “Parallel-Processing Techniques for Automatic Test Pattern Generation,” IEEE Computer, pp. 71–84, 1992.

    Google Scholar 

  2. B. Ramkumar and P. Banerjee, “Portable Parallel Test Generation for Sequential Circuits,” in Proceedings IEEE/ACM International Conference on Computer-Aided Design, pp. 220–223, 1992.

    Google Scholar 

  3. P. Agrawal, V. D. Agrawal, and J. Villoldo, “Sequential Circuit Test Generation on a Distributed System,” in Proceedings IEEE/ACM Design Automation Conference, pp. 107–111, 1993.

    Google Scholar 

  4. P. A. Krauss and K. J. Antreich, Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits, vol. Parallel Computer Architectures: Theory, Hardware, Software, Applications of Lecture Notes in Computer Science No. 732, pp. 234–245. Springer-Verlag, 1993.

    Google Scholar 

  5. S. B. Akers and B. Krishnamurthy, “Test Counting: A Tool for VLSI Testing,” IEEE Design & Test of Computers, pp. 58–73, 1989.

    Google Scholar 

  6. S. Patil and P. Banerjee, “Fault Partitioning Issues in an Integrated Parallel Test Generation / Fault Simulation Environment,” in Proceedings IEEE International Test Conference, pp. 718–726, 1989.

    Google Scholar 

  7. R. Butler and E. Lusk, “User's Guide to the p4 Parallel Programming System,” Tech. Rep. ANL-92/17, Argonne National Laboratory, Mathematics and Computer Science Division, 1992.

    Google Scholar 

  8. F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” in Proceedings IEEE International Symposium on Circuits and Systems, pp. 1929–1934, 1989.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, Germany

    Peter A. Krauss

Authors
  1. Peter A. Krauss
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Wolfgang Gentzsch Uwe Harms

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Krauss, P.A. (1994). A distributed automatic test pattern generation system. In: Gentzsch, W., Harms, U. (eds) High-Performance Computing and Networking. HPCN-Europe 1994. Lecture Notes in Computer Science, vol 796. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0020356

Download citation

  • DOI: https://doi.org/10.1007/BFb0020356

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-57980-9

  • Online ISBN: 978-3-540-48406-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation