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TOP-1 multiprocessor workstation

  • Part II Parallel Lisp Systems and Architectures
  • Conference paper
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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 441))

Abstract

IBM Tokyo Research Laboratory developed a high-performance multiprocessor workstation, TOP-1, which is currently running with a multi-threaded multiprocessor version of AIX operating system, as a research prototype to study and clarify the multiprocessor architecture design points as well as to study operating systems, compilers, and application programs for multiprocessor workstations.

The novel architectural features of TOP-1 are the 2-way interleaved dual bus for providing wider bus bandwidth, the effective message broadcasting mechanism for asynchronous communications, the mechanism to allow several different snoop protocols to coexist at a time, and the high-speed and fair arbitration mechanism. In particular, it has a statistics unit that enables us to obtain statistics on operating system and application programs running on the real machine.

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References

  1. R. R. Atkinson and E. M. McCreight,The Dragon Processor,Proceedings of Second Int'l Conference on ASPLOS, pp. 65–69, 1987.

    Google Scholar 

  2. C. P. Thacker and L. C. Stewart, Firefly: a Multi-Processor Workstation,Proceeding of Second Int'l Conference on ASPLOS, pp. 164–172,1987.

    Google Scholar 

  3. R. Katz, et.al., Implementing a Cache Consistency Protocol,Proceedings of the 12th Int'l Symp. on Computer Architecture, IEEE, pp. 276–283,1985.

    Google Scholar 

  4. J. R. Goodman, Using Cache Memory to Reduce Processor-Memory Traffic, Proceedings of the 10th Int'l Symp. on Computer Architecture, IEEE, p. 124–131,1983.

    Google Scholar 

  5. J. Archiballd and J. L. Baer, Cache Coherence Protoocos: Evaluation Using a Multiprocessor SimulationModel,ACM Trans. on Computer Systems, Vol. 4, No. 4, pp. 273–298,1986.

    Google Scholar 

  6. R. L. Lee, et.al., Multiprocessor Cache Design Considerations, Proceedings of the 14th Annual Int'l Symp. on Computer Architecture, pp. 253–262,1987.

    Google Scholar 

  7. S. J. Eggers and R. H. Katz, A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation,Proceedings of the 15th Annual Int'l Symp. on Coomputer Architecture, pp. 373–382, 1988.

    Google Scholar 

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Takayasu Ito Robert H. Halstead Jr.

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© 1990 Springer-Verlag Berlin Heidelberg

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Suzuki, N. (1990). TOP-1 multiprocessor workstation. In: Ito, T., Halstead, R.H. (eds) Parallel Lisp: Languages and Systems. PSC 1989. Lecture Notes in Computer Science, vol 441. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0024168

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  • DOI: https://doi.org/10.1007/BFb0024168

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-52782-4

  • Online ISBN: 978-3-540-47143-1

  • eBook Packages: Springer Book Archive

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