Abstract
We present an application specific, asynchronous VLSI processor array for the dynamic programming algorithm for the 0/1 knapsack problem. The array is derived systematically, using correctnesspreserving transformations, in two steps: the standard (dense) algorithm is first transformed into an irregular (sparse) functional program which has better efficiency. This program is then implemented as a modular VLSI architecture with nearest neighbor connections. Proving bounds on buffer sizes yields a linear array of identical asynchronous processors, each with simple computational logic and a pair of fixed size FIFOs. A modular solution can be obtained by additional load-time control, enabling the processors to pool their buffers.
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© 1996 Springer-Verlag Berlin Heidelberg
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de Dinechin, F., Wilde, D.K., Rajopadhye, S., Andonov, R. (1996). A regular VLSI array for an irregular algorithm. In: Ferreira, A., Rolim, J., Saad, Y., Yang, T. (eds) Parallel Algorithms for Irregularly Structured Problems. IRREGULAR 1996. Lecture Notes in Computer Science, vol 1117. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0030109
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DOI: https://doi.org/10.1007/BFb0030109
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