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Hierarchical verification of two-dimensional high-speed multiplication in PVS: A case study

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Book cover Formal Methods in Computer-Aided Design (FMCAD 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1166))

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Abstract

It is shown how to use the PVS specification language and proof checker to present a hierarchical formalization of a two-dimensional, high-speed integer multiplier on the gate level. We first give an informal description of iterative array multiplier circuits together with a natural refinement into vertical and horizontal stages, and then show how the various features of PVS can be used to obtain a readable, high-level specification. The verification exploits the tight integration between rewriting, arithmetic decision procedures, and equality that is present in PVS. Altogether, this case study demonstrates that the resources of an expressive specification language and of a general-purpose theorem prover permit highly automated verification in this domain, and can contribute to clarity, generality, and reuse.

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Authors and Affiliations

  1. Abtl. Künstliche Intelligenz, Universität Ulm, D-89069, Ulm, Germany

    Harald Rueß

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  1. Harald Rueß
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Mandayam Srivas Albert Camilleri

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© 1996 Springer-Verlag Berlin Heidelberg

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Rueß, H. (1996). Hierarchical verification of two-dimensional high-speed multiplication in PVS: A case study. In: Srivas, M., Camilleri, A. (eds) Formal Methods in Computer-Aided Design. FMCAD 1996. Lecture Notes in Computer Science, vol 1166. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0031801

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  • DOI: https://doi.org/10.1007/BFb0031801

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61937-6

  • Online ISBN: 978-3-540-49567-3

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