Automated logic synthesis

Abstract

It is unlikely that we will be able to utilize the full potential of VLSI without major improvements in designer productivity. One approach is to design at a higher functional level and to generate acceptable implementations automatically from such functional specifications. Previous attempts at automatic logic generation have usually produced results that were much more expensive than manual implementation and have relied on exponential 2-level minimization algorithms which will not scale to VLSI designs. We are exploring an approach based on local transformations with nearly linear run times. A system using these ideas has been built and used to synthesize several gate-array chips with encouraging results. This system has been extended to remap implementations to a different technology and to generate alternative PLA and gate networks for different performance requirements.