Abstract
In this paper, we present an optimized design flow to map Register-Transfer-Level (RTL) netlists onto multiple-FPGA architectures. Our FPGA-dedicated method fully exploits design structure by letting the basic design steps technology mapping, hierarchical partitioning, floorplanning and signal flow driven placement, interact. This efficiently reduces runtime and yields design implementations of higher performance and better resource utilization than published before.
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Stohmann, J., Harbich, K., Olbrich, M., Barke, E. (1998). An optimized design flow for fast FPGA-based rapid prototyping. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055235
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DOI: https://doi.org/10.1007/BFb0055235
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