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A knowledge-based system for prototyping on FPGAs

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1482))

Abstract

This paper presents a knowledge-based system for ASIC prototyping on FPGAs. ASIC prototyping is known to be a difficult task. The rapid increase of densities and speeds of FPGAs, as well as sophisticated architectural features require changes in prototyping methodologies. FPGA prototypes should often work at real speeds. Obtaining efficient implementations demands reach design experience and perfect knowledge of the FPGA technology. The interest is in accumulating knowledges and reusing parts of previous designs. The idea was to facilitate prototyping by creating the knowledge-based system which stores the designer skills in form of technology-dependent design rules and reuse blocks.

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References

  1. Krupnova, H., Abbara, A., Saucier, G.: A Hierarchy-Driven FPGA Partitioning Method. Proc. 34-th ACM/IEEE Design Automation Conference (1997) 522–525

    Google Scholar 

  2. Altera Data Book: FLEX 10K Embedded Programmable Logic Family Data Sheet (1996)

    Google Scholar 

  3. Lehmann, G., Wunder, B. Muller Glaser K. D.: A VHDL Reuse Workbench. Proc. EURO-DAC (1996) 412–417

    Google Scholar 

  4. Jha, P. K., Dutt, N. D.: Design Reuse through High-Level Library Mapping. Proc. of the European Design and Test Conference (1995) 345–350

    Google Scholar 

  5. Girczyc, E., Carlson, S.: Increasing Design Quality and Engineering Productivity through Design Reuse. Proc. 30th ACM/IEEE Design Automation Conference (1993) 48–53

    Google Scholar 

  6. Mariatos, V., Senouci, S-A., Bertrand, M. C., Saucier, G., Kikides, J.: A Library of Reuse Blocks for FPGAs. Proc. European Design&Test Conference, User Forum volume (1997) 609–633

    Google Scholar 

  7. Lytle, C., Beachler, R.K.: Using Intellectual Property in Programmable Logic. Proc. European Design&Test Conference, User Forum volume (1997): 125–129

    Google Scholar 

  8. Altera AMPP Catalog (1997)

    Google Scholar 

  9. VSI Alliance: Architecture Document. http://www.vsi.org/library.html (1997)

    Google Scholar 

  10. Altera Application Note 66: Implementing FIFO Buffers in FLEX 10K Devices (1996)

    Google Scholar 

  11. Altera Application Note 52: Implementing RAM Functions in FLEX 10K Devices (1995)

    Google Scholar 

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Reiner W. Hartenstein Andres Keevallik

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© 1998 Springer-Verlag Berlin Heidelberg

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Krupnova, H., Dinh, V.D., Saucier, G. (1998). A knowledge-based system for prototyping on FPGAs. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055236

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  • DOI: https://doi.org/10.1007/BFb0055236

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64948-9

  • Online ISBN: 978-3-540-68066-6

  • eBook Packages: Springer Book Archive

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