CAD system for ASM and FSM synthesis

Abstract

For hardware realization of computer programs (for the realization of software as hardware) it is very important to represent, to transform and to synthesize very complex Finite State Machines (FSM). This work contains the first report about CAD system Synthesis 1 for design of FSMs with hardly any constraints on their size, that is, the number of inputs, outputs and states. Synthesis 1 implements automatically various transformations of an Algorithmic State Machine (minimization, composition, decomposition etc.) and synthesis of FSM's logic circuit as (a) multilevel circuit with gates from a predefined library; (b) with standard LSI and VLSI circuits without memory, such as PLA(s,t,q) — programmable logic arrays with s inputs, t outputs and q horizontals; (c) with standard LSI and VLSI circuits with memory, such as PLAM(s,t,q,r) — programmable logic arrays with s inputs, t outputs, q horizontals and r memory elements; (d) matrices circuits on the chip with a minimization of the chip area; (e) with LUTs (Look-Up-Tables) for FPGA technology.