Abstract
Boolean satisfiability (SAT) is a core computer science problem with many important commercial applications. An NP-complete problem, many different approaches for accelerating SAT either in hardware or software have been proposed. In particular, our prior work studied mechanisms for accelerating SAT using configurable hardware to implement formula-specific solver circuits. In spite of this progress, SAT solver runtimes still show room for further improvement.
In this paper, we discuss further improvements to configurable-hardware-based SAT solvers. We discuss how dynamic techniques can be used to add the new solver circuitry to the hardware during run-time. By examining the basic solver structure, we explore how it can be best designed to support such dynamic reconfiguration techniques. These approaches lead to several hundred times speedups for many problems. Overall, this work offers a concrete example of how aggressively employing on-the-fly reconfigurability can enable runtime learning processes in hardware. As such, this work opens new opportunities for high performance computing using dynamically reconfigurable hardware.
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© 1998 Springer-Verlag Berlin Heidelberg
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Zhong, P., Martonosi, M., Ashar, P., Malik, S. (1998). Solving boolean satisfiability with dynamic hardware configurations. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055260
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DOI: https://doi.org/10.1007/BFb0055260
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