Skip to main content

Accelerating DTP with reconfigurable computing engines

  • Miscellaneous
  • Conference paper
  • First Online:
  • 288 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1482))

Abstract

This paper describes how a reconfigurable computing engine can be used to accelerate DTP functions. We show how PostScript rendering can be accelerated using a commercially available FPGA co-processor card. Our method relies on dynamically swapping in pre-computed circuits to accelerate the compute intensive portions of PostScript rendering.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Adobe Systems. Adobe PostScript Extreme White Paper. Adobe 1997

    Google Scholar 

  2. Adobe Systems. Adobe PrintGear Technology Backgrounder. Adobe 1997

    Google Scholar 

  3. M. Sheeran, G. Jones. Circuit Design in Ruby. Formal Methods for VLSI Design, J. Stanstrup, North Holland, 1992.

    Google Scholar 

  4. Satnam Singh and Pierre Bellec. Virtual Hardware for Graphics Applications using FPGAs. FCCM'94. IEEE Computer Society, 1994.

    Google Scholar 

  5. Satnam Singh. Architectural Descriptions for FPGA Circuits. FCCM'95. IEEE Computer Society. 1995.

    Google Scholar 

  6. J.D. Foley, A. Van Dam. Computer Graphics: Principles and Practice. Addison Wesley. 1997.

    Google Scholar 

  7. Xilinx. XC6200 FPGA Family Data Sheet. Xilinx Inc. 1995.

    Google Scholar 

  8. S Singh, J. Patterson, J. Burns, M Dales. PostScript rendering using virtual hardware. FPL'97. Springer, 1997

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Reiner W. Hartenstein Andres Keevallik

Rights and permissions

Reprints and permissions

Copyright information

© 1998 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

MacVicar, D., Singh, S. (1998). Accelerating DTP with reconfigurable computing engines. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055267

Download citation

  • DOI: https://doi.org/10.1007/BFb0055267

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64948-9

  • Online ISBN: 978-3-540-68066-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics