Abstract
A method of calculating the 3x3 mask convolution required for many low level image processing algorithms is presented, which is well suited for implementing on reconfigurable FPGAs. The approach is based on distributed arithmetic, and uses the symmetry of weights present in many filter masks to save on circuit space, at the expense of requiring custom circuitry for each set of coefficients. A four product example system has been implemented on a Xilinx XC6216 device to demonstrate the suitability of this reconfigurable architecture for image processing systems.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Jaggernauth, J., Loui, A.C.P., Venetsanopoulos, A.N.: “Real-Time Image Processing by Distributed Arithmetic Implementation of Two-Dimensional Digital Filters”, IEEE Trans. ASSP, Vol. ASSP-33, No. 6, pp. 1546–155, Dec. 1985
Goslin, G.R.: “Using Xilinx FPGAs to design custom digital signal processing devices”, available at http://www.xilinx.com/appnotes/dspx5dev.htm
Mintzer, L.:”FIR Filters with Field-Programmable Gate Arrays”, Journal of VLSI Signal Processing, Vol. 6, pp.119–127, 1993
Xilinx Inc., “XC6200 field programmable gate arrays”, available at http://www.xilinx.com/partinfo/6200_OnlinePDF.pdf
Xilinx Inc., “A fast constant coefficient multiplier for the XC6200”, available at http://www.xilinx.com/xapp/xapp082_OnlinePDF.pdf
Duncan, A., Kean, T: “DES keybreaking, encryption and decryption on the XC6216”, Proc. 6th Annual IEEE Symposium on Custom Computing Machines, 1998
Wirth, N.: “Digital circuit design”, Springer-Verlag Berlin Heidelberg, 1995
Singh, S, Slous, R.: “Accelerating Adobe Photoshop with reconfigurable logic” Proc. 6th Annual IEEE Symposium on Custom Computing Machines, 1998
Hauck, S, Z. Li, Schwabe, E.: “Configuration compression for the Xilinx XC6200 FPGA” Proc. 6th Annual IEEE Symposium on Custom Computing Machines, 1998
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1998 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Cerro-Prada, E., James-Roxby, P.B. (1998). High speed low level image processing on FPGAs using distributed arithmetic. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055276
Download citation
DOI: https://doi.org/10.1007/BFb0055276
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-64948-9
Online ISBN: 978-3-540-68066-6
eBook Packages: Springer Book Archive