A flexible implementation of high-performance FIR filters on Xilinx FPGAs

Abstract

Finite impulse-response filters (FIR filters) are very commonly used in digital signal processing applications and traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on an FPGA, i. e., logic blocks and flip flops, and furthermore, the high routing delays, require compact implementations of the circuits. Hence, in lookup table-based FPGAs, e. g. Xilinx FPGAs, FIR-filters were implemented usually using distributed arithmetic. However, such filters can only be used where the filter coefficients are constant. In this paper, we present approaches for a more flexible FPGA implementation of FIR filters. Using pipelined multipliers which are carefully adapted to the underlying FPGA structure, our FIR filters do not require a predefinition of the filter coefficients. Combining pipelined multipliers and parallely distributed arithmetic results in different trade-offs between hardware cost and flexibility of the filters. We show that clock frequencies of up to 50 MHz are achievable using Xilinx XCAOxx — 5 FPGAs.