Abstract
An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16 bit address space into an 8 bit one. This circuit, based on FPGAs, is readily applicable to the design of set-associative cache memories. Possible use the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.
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Damiani, E., Liberali, V., Tettamanzi, A.G.B. (1998). Evolutionary design of hashing function circuits using an FPGA. In: Sipper, M., Mange, D., Pérez-Uribe, A. (eds) Evolvable Systems: From Biology to Hardware. ICES 1998. Lecture Notes in Computer Science, vol 1478. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0057605
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DOI: https://doi.org/10.1007/BFb0057605
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