Abstract
In multi-tasking real-time systems, inter-task cache interference due to preemptions degrades system performance and predictability, complicating system design and analysis. To address this problem, we propose a novel scheduling scheme, called LPS (Limited Preemptible Scheduling), that limits preemptions to predetermined points with small cache-related preemption costs. We also give an accompanying analysis method that determines the schedulability of a given task set under LPS. By limiting preemption points, the proposed LPS scheme reduces preemption costs and thus increases the system throughput. Experimental results show that LPS can increase schedulable utilization by more than 10 % and save processor time by up to 44 % as compared with a traditional fully preemptible scheduling scheme.
Preview
Unable to display preview. Download preview PDF.
References
R. Arnold, F. Mueller, D. B. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In Proceedings of the 15th Real-Time Systems Symposium, pages 172–181, Dec. 1994.
C. A. Healy, D. B. Whalley, and M. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of the 16th Real-Time Systems Symposium, pages 288–297, Dec. 1994.
Y. Hur, Y. H. Bae, S.-S. Lim, S.-K. Kim, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, and C. S. Kim. Worst case timing analysis of RISC processors: R3000/R3010 case study. In Proceedings of the 16th Real-Time Systems Symposium, pages 308–321, Dec. 1995.
M. Joseph and P. Pandya. Finding response times in a real-time system. The BCS Computer Journal, 29(5):390–395, Oct. 1986.
D. B. Kirk. SMART (strategic memory allocation for real-time) cache design. In Proceedings of the 10th Real-Time Systems Symposium, pages 229–237, Dec. 1989.
C.-G. Lee, J. Hahn, Y.-M. Seo, S. L. Min, R. Ha, S. Hong, C. Y. Park, M. Lee, and C. S. Kim. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In Proceedings of the Seventeenth Real-Time Systems Symposium, pages 264–274, Dec. 1996.
Y. T. S. Li, S. Malik, and A. Wolfe. Efficient microarchitecture modeling and path analysis for real-time software. In Proceedings of the 16th Real-Time Systems Symposium, pages 298–307, Dec. 1995.
S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, S.-M. Moon, and C. S. Kim. An accurate worst case timing analysis for RISC processors. IEEE Transactions on Software Engineering, 21(7):593–604, Jul. 1995.
J. Simonson. Cache Memory Management in Real-Time Systems. PhD thesis, University of Illinois at Urbana-Champaign, Sep. 1996.
K. Tindell, A. Burns, and A. Wellings. An extendible approach for analyzing fixed priority hard real-time tasks. The Journal of Real-Time Systems, 6(2):133–151, Mar. 1994.
A. Wolfe. Software-based cache partitioning for real-time applications. In Proceedings of the 3rd International Workshop on Responsive Computer Systems, Sep. 1993.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1998 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lee, S., Lee, CG., Lee, M., Min, S.L., Kim, C.S. (1998). Limited preemptible scheduling to embrace cache memory in real-time systems. In: Mueller, F., Bestavros, A. (eds) Languages, Compilers, and Tools for Embedded Systems. LCTES 1998. Lecture Notes in Computer Science, vol 1474. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0057780
Download citation
DOI: https://doi.org/10.1007/BFb0057780
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-65075-1
Online ISBN: 978-3-540-49673-1
eBook Packages: Springer Book Archive