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Mechanizing verification of arithmetic circuits: SRT division

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1346))

Abstract

The use of a rewrite-based theorem prover for verifying properties of arithmetic circuits is discussed. A prover such as Rewrite Rule Laboratory (RRL) can be used effectively for establishing numbertheoretic properties of adders, multipliers and dividers. Since verification of adders and multipliers has been discussed elsewhere in earlier papers, the focus in this paper is on a divider circuit. An SRT division circuit similar to the one used in the Intel Pentium processor is mechanically verified using RRL. The number-theoretic correctness of the division circuit is established from its equational specification. The proof is generated automatically, and follows easily using the inference procedures for contextual rewriting and a decision procedure for the quantifier-free theory of numbers (Presburger arithmetic) already implemented in RRL. Additional enhancements to rewrite-based provers such as RRL that would further facilitate verifying properties of circuits with structure similar to that of the SRT division circuit are discussed.

Partially supported by the National Science Foundation Grant no. CCR-9712366.

This work was done while the author was at State University of New York, Albany.

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References

  1. R.E. Bryant, Bit-level Analysis of an SRT Divider Circuit. Tech. Rep. CMU-CS-95-140, Carnegie Mellon University, April 1995.

    Google Scholar 

  2. E.M. Clarke, S.M. German and X. Zhao, “Verifying the SRT division algorithm using theorem proving techniques,” Proc. Computer Aided Verification, 8th Intl. Conf. —CAV'96, New Brunswick, July/August 1996, Springer LNCS 1102 (eds. Alur and Henzinger), 111–122.

    Google Scholar 

  3. M.D. Ercegovac and T. Lang, Division and Square Root: Digit Recurrence Algorithms and Implementations. Kluwer, 1994.

    Google Scholar 

  4. S. German, Towards Automatic Verification of Arithmetic Hardware. Lecture Notes, 1995.

    Google Scholar 

  5. D. Kapur, “Rewriting, decision procedures and lemma speculation for automated hardware verification,” Proc. 10th Intl. Conf. Theorem Proving in Higher Order Logics, LNCS 1275 (eds. Gunter and Felty), Murray Hill, NJ, Aug 1997, 171–182.

    Google Scholar 

  6. D. Kapur and X. Nie, “Reasoning about numbers in Tecton,” Proc. 8th Intl. Symp. Methodologies for Intelligent Systems, (ISMIS'94), Charlotte, North Carolina, October 1994, 57–70.

    Google Scholar 

  7. D. Kapur and M. Subramaniam, “Mechanically verifying a family of multiplier circuits,” Proc. Computer Aided Verification, 8th Intl. Conf. —CAV'96, New Brunswick, July/August 1996, Springer LNCS 1102 (eds. Alur and Henzinger), 1996, 135–146.

    Google Scholar 

  8. D. Kapur and M. Subramaniam, “Mechanical verification of adder circuits using powerlists,” Dept. of Computer Science Tech. Report, SUNY Albany, November 1995. Accepted for publication in J. of Formal Methods in System Design.

    Google Scholar 

  9. D. Kapur and M. Subramaniam, “Lemma discovery in automating induction,” Proc. Intl. Conf. on Automated Deduction, CADE-13, LNAI 1104 (eds. McRobbie and Slaney), New Jersey, July 1996.

    Google Scholar 

  10. D. Kapur and M. Subramaniam, “Intermediate lemma generation from circuit descriptions,” under preparation, State University of New York, Albany, NY, October 1997.

    Google Scholar 

  11. D. Kapur, and H. Zhang, “An overview of Rewrite Rule Laboratory (RRL),” J. of Computer and Mathematics with Applications, 29, 2, 1995, 91–114.

    Article  MathSciNet  Google Scholar 

  12. M. Leeser and J.O'Leary, “Verification of a subtractive radix-2 square root algorithm and implementation,” Proc. ICCD'95, IEEE Computer Society Press, 1995, 526–531.

    Google Scholar 

  13. P.S. Miner and J.F. Leathrum Jr., “Verification of IEEE compliant subtractive division algorithm,” Proc. FMCAD'96, Palo Alto, CA, 1996.

    Google Scholar 

  14. J Moore, T. Lynch and M. Kaufmann, A Mechanically Checked Proof of the Correctness of the AMD5K86 Floating Point Division Algorithm. CL Inc. Technical Report, March 1996.

    Google Scholar 

  15. S.F. Obermann and M.J. Flynn, An Analysis of Division Algorithms and Implementations. Technical Report CSL-TR-95-675, Stanford University, July 1995.

    Google Scholar 

  16. A.R. Omondi, Computer Arithmetic Systems: Algorithms, Architecture and Implementations, Prentice Hall 1994.

    Google Scholar 

  17. J.E. Robertson, “A new class of digital division methods,” IRE Transactions on Electronic Computers, 1958, 218–222.

    Google Scholar 

  18. H. Ruess, N. Shankar and M.K. Srivas, “Modular verification of SRT division,” Proc. Computer Aided Verification, 8th Intl. Conf. —CAV'96, New Brunswick, July/August 1996, Springer LNCS 1102 (eds. Alur and Henzinger), 123–134.

    Google Scholar 

  19. K.D. Tocher, “Techniques of multiplication and division for automatic binary computers,” Quarterly Journal of Mechanics and Applied Mathematics, 11(3), 1958.

    Google Scholar 

  20. G.S. Taylor, “Compatible hardware for division and square root,” Proc. 5th IEEE Symp. on Computer Architecture, May 1981.

    Google Scholar 

  21. D. Verkest, L. Claesen, and H. De Man, “A proof of the nonrestoring division algorithm and its implementation on an ALU,” J. Formal Methods in System Design, 4, Jan. 1994, 5–31.

    Article  MATH  Google Scholar 

  22. T.E. Williams and M. Horowitz, “A 160nS 54-bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages,” Proc. 10th IEEE Symp. on Computer Arithmetic, 1991.

    Google Scholar 

  23. H. Zhang, “Implementing contextual rewriting,” Proc. 3rd Intl. Workshop on Conditional Term Rewriting Systems, Springer LNCS 656 (eds. Remy and Rusinowitch), 1992, 363–377.

    Google Scholar 

  24. H. Zhang, D. Kapur, and M.S. Krishnamoorthy, “A mechanizable induction principle for equational specifications,” Proc. 9th Intl. Conf. Automated Deduction (CADE), Springer LNCS 310, (eds. Lusk and Overbeek), Chicago, 1988, 250–265.

    Google Scholar 

  25. Proc. of Eighth Symp. of HOT Chips, IEEE Computer Society, California, 1996.

    Google Scholar 

  26. Proc. of Ninth Symp. of HOT Chips, IEEE Computer Society, California, 1997.

    Google Scholar 

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S. Ramesh G Sivakumar

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© 1997 Springer-Verlag Berlin Heidelberg

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Kapur, D., Subramaniam, M. (1997). Mechanizing verification of arithmetic circuits: SRT division. In: Ramesh, S., Sivakumar, G. (eds) Foundations of Software Technology and Theoretical Computer Science. FSTTCS 1997. Lecture Notes in Computer Science, vol 1346. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0058026

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  • DOI: https://doi.org/10.1007/BFb0058026

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63876-6

  • Online ISBN: 978-3-540-69659-9

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