Abstract
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Arno92] [Butt92] [Hauc94] [Apti96] [Vuil96] [Babb97] and previous research has shown that the partial crossbar is one of the best existing architectures [Kim96] [Khal97]. Recently, the Hybrid Complete-Graph Partial-Crossbar Architecture (HCGP) was proposed [Khal98], which was shown to be superior to the Partial Crossbar. In this paper we propose a new routing architecture, called the Hardwired-Clusters Partial-Crossbar (HWCP) which is better suited for large MFSs implemented using multiple boards. The HWCP architecture is compared to the HCGP and Partial Crossbar and we show that it gives substantially better manufacturability. We compare the performance and cost of the HWCP, HCGP and Partial Crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. We show that the HWCP architecture gives reasonably good cost and speed compared to the HCGP and Partial Crossbar architectures.
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[Apti96] Aptix Corporation, Product brief: The System Explorer MP4, 1996. Available on Aptix Web site: http://www.aptix.com.
[Arno92] J. M. Arnold, D. A. Buell, and E. G. Davis, “Splash 2,” Proceedings of 4th Annual ACM Symposium on Parallel Algorithms and Architectures, pp. 316–322, 1992.
[Babb97] J. Babb et al., “Logic Emulation with Virtual Wires,” IEEE Trans. on CAD, vol. 16, no. 6, pp. 609–626, June 1997.
[Brow92] S. Brown, R. Francis, J. Rose, and Z. Vranesic, Field Programmable Gate Arrays, Kluwer Academic Publishers, 1992.
[Butt92] M. Butts, J. Batcheller, and J. Varghese, “An Efficient Logic Emulation System,” Proceedings of IEEE International Conference on Computer Design, pp. 138–141, 1992.
[Hauc94] S. Hauck, G. Boriello, C. Ebeling, “Mesh Routing Topologies for Multi-FPGA Systems”, Proceedings of International Conference on Computer Design (ICCD’94), pp. 170–177, 1994.
[ICub97] I-Cube, Inc., The IQX Family Data Sheet, May 1997. Available at: www.icube.com.
[Khal97] M. A. S. Khalid and J. Rose, “Experimental Evaluation of Mesh and Partial Crossbar Routing Architectures for Multi-FPGA Systems,” Proceedings of the Sixth IFIP International Workshop on Logic and Architecture Synthesis (IWLAS’97), pp. 119–127, 1997.
[Khal98] M. A. S. Khalid and J. Rose, “A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems,” Proc. of 1998 Sixth ACM International Symposium on Field-Programmable Gate Arrays (FPGA’98), pp. 45–54, February 1998. This paper is available on the internet at “www.eecg.toronto.edu/~khalid/papers/fpga98.ps”.
[Khal99] M. A. S. Khalid, Routing Architecture and Layout Synthesis for Multi-FPGA Systems, Ph. D. Thesis, University of Toronto, Toronto, Canada, 1999.
[Kim96] C. Kim, H. Shin, “A Performance-Driven Logic Emulation System: FPGA Network Design and Performance-Driven Partitioning,” IEEE Trans. on CAD, vol. 15, no. 5, pp. 560–568, May 1996.
[Iers97] M. Van Ierssel, University of Toronto, Private Communication, 1997.
[Quic96] Quickturn Design Systems, Inc., System Realizer Data Sheet, 1996. Available on Quickturn Web site:http://www.quickturn.com.
[Vuil96] J. E. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, and P. Boucard, “Programmable Active Memories: Reconfigurable Systems Come of Age,” IEEE Transactions on VLSI, Vol 4, No. 1, pp. 56–69, March 1996.
[Xili97] Xilinx, Inc., Product Specification: XC4000E and XC4000X Series FPGAs, Version 1.2, June 16, 1997. Available on Xilinx Web site: www.xilinx.com.
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© 1999 Springer-Verlag
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Khalid, M.A.S., Rose, J. (1999). Hardwired-clusters partial-crossbar: A hierarchical routing architecture for multi-FPGA systems. In: Rolim, J., et al. Parallel and Distributed Processing. IPPS 1999. Lecture Notes in Computer Science, vol 1586. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0097944
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DOI: https://doi.org/10.1007/BFb0097944
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