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FPGA Based High Performance Double-Precision Matrix Multiplication

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Abstract

We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, optimized for implementation on high-end FPGAs. It forms the kernel in many important tile-based BLAS algorithms, making an excellent candidate for acceleration. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs, the trade-offs involved in terms of local-memory and bandwidth for an FPGA implementation are demonstrated and an analysis is presented for the optimal choice of design parameters. The designs, implemented on a Virtex-5 SX240T FPGA, scale gracefully from 1 to 40 processing elements(PEs) with a less than 1% degradation in the design frequency of 373 MHz. With 40 PEs and a design speed of 373 MHz, a sustained performance of 29.8 GFLOPS is possible with a bandwidth requirement of 750 MB/s for design-II and 5.9 GB/s for design-I. This compares favourably with both related art and general purpose CPU implementations.

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Authors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, 400076, India

    Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar & H. Narayanan

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  1. Vinay B. Y. Kumar
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  2. Siddharth Joshi
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  3. Sachin B. Patkar
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  4. H. Narayanan
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Correspondence to Vinay B. Y. Kumar.

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Kumar, V.B.Y., Joshi, S., Patkar, S.B. et al. FPGA Based High Performance Double-Precision Matrix Multiplication. Int J Parallel Prog 38, 322–338 (2010). https://doi.org/10.1007/s10766-010-0131-8

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  • DOI: https://doi.org/10.1007/s10766-010-0131-8

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