Abstract
In this paper, a low power digital baseband to be used together with impulse-radio ultra wideband radio frequency front-end has been presented. It can provide received pulse synchronization required for burst mode and low power operation. It also overcomes clock drift issue between different transceivers. The clock and data recovery is implemented fully in digital domain without the need of conventional phase-locked loop, delay locked loop or analog-to-digital converter. The chip is designed using 0.18 μm CMOS technology. It consumes 5 mW and can recover data up to 20 Mbps.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
Abbreviations
- ADC:
-
Analog-to-digital converter
- BER:
-
Bit error rate
- CDR:
-
Carrier data recovery
- DLL:
-
Delay-locked loop
- FSM:
-
Finite state machine
- HDL:
-
Hardware description language
- IR:
-
Impulse radio
- LFSR:
-
Linear feedback shift register
- LNA:
-
Low noise amplifier
- MAC:
-
Medium access control
- MCU:
-
Micro-controller unit
- NRZ:
-
Non-return-to-zero
- OOK:
-
On-off keying
- PLL:
-
Phase-locked loop
- PN:
-
Pseudorandom number
- RF:
-
Radio frequency
- RX:
-
Receiver
- RZ:
-
Return-to-zero
- SPI:
-
Serial peripheral interface
- TX:
-
Transmitter
- UWB:
-
Ultra wideband
- VCO:
-
Voltage controlled oscillator
- WPAN:
-
Wireless personal area network
- WSN:
-
Wireless sensor network
References
R. Blazquez, P. Newaskar, F. Lee, A. Chandrakasan, A baseband processor for pulsed ultra-wideband signals, in Proc. CICC (2004), pp. 587–590
D.C. Daly, A.P. Chandrakasan, An energy-efficient OOK transceiver for wireless sensor networks. IEEE J. Solid-State Circuits 42, 1003–1011 (2007)
S. Diao, Y. Zheng, C.H. Heng, A CMOS ultra low-power and highly efficient UWB-IR transmitter for WPAN applications. IEEE Trans. Circuits Syst. II 56, 200–204 (2009)
R. Farjad-Rad, A. Nguyen, J. Tran, T. Greer, J. Poulton, W.J. Dally, J.H. Edmondson, R. Senthinathan, R. Rathi, M.J.E. Lee, H.T. Ng, A 33 mW 8 Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid-State Circuits 39, 1553–1561 (2004)
Y. Gao, Y. Zheng, C.H. Heng, Low-Power CMOS RF front-end for non-coherent IR-UWB receiver, in Proc. ESSCIRC (2008), pp. 386–389
P.K. Hanumolu, G.Y. Wei, U.K. Moon, A wide-tracking range clock and data recovery circuit. IEEE J. Solid-State Circuits 43, 425–439 (2008)
P. Larsson, A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability. IEEE J. Solid-State Circuits 34, 1951–1960 (1999)
F.S. Lee, A.P. Chandrakasan, A 2.5 nJ/bit 0.65 V pulsed UWB receiver in 90 nm CMOS. IEEE J. Solid-State Circuits 42, 2851–2859 (2007)
C.K. Liang, R.J. Yang, S.I. Liu, An all-digital fast-locking programmable DLL-based clock generator. IEEE Trans. Circuits Syst. I 55, 261–269 (2007)
I. O’Donnell, S. Chen, S. Wang, R. Brodersen, An integrated, low power, ultra-wideband transceiver architecture for low-rate, indoor wireless systems, in Proc. IEEE CAS Workshop on Wireless Communications and Networking (2002), pp. 1623–1631
J. Ryckaert et al., A CMOS ultra-wideband receiver for low data-rate communications. IEEE J. Solid-State Circuits 42, 2515–2527 (2007)
T. Terada, S. Yoshizumi, M. Muqsith, Y. Sanada, T. Kuroda, A CMOS ultra-wideband impulse radio transceiver for 1-Mb/s data communications and ±2.5-cm range finding. IEEE J. Solid-State Circuits 41, 891–898 (2006)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Toh, W.D., Zheng, Y. & Heng, CH. Low Power Digital Baseband for Impulse Radio Ultra-Wideband Transceiver. Circuits Syst Signal Process 31, 223–235 (2012). https://doi.org/10.1007/s00034-010-9249-6
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-010-9249-6