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FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation

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Abstract

This paper presents a FPGA-based rapid prototyping of an adaptive noise canceller (ANC) using XUP Virtex-II Pro development board and Xilinx System Generator. New parallel and sequential architectures of the ANC are proposed and successfully applied to remove noise from electrocardiogram and speech signals. The pipelined architecture were evaluated and compared to existing high-speed systems using objective measurement tests. By providing comparable filtering performances that of the parallel architectures, the proposed sequential system required fewer material resources.

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Authors and Affiliations

  1. Department of Engineering, Université du Québec à Rimouski, 300, allée des Ursulines, Rimouski, Qc, Canada, G5L 3A1

    Mohammed Bahoura

  2. Department of Applied Sciences, Université du Québec à Chicoutimi, 550, boul. de l’Université, Chicoutimi, Qc, Canada, G7H 2B1

    Hassan Ezzaidi

Authors
  1. Mohammed Bahoura
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  2. Hassan Ezzaidi
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Correspondence to Mohammed Bahoura.

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Bahoura, M., Ezzaidi, H. FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation. Circuits Syst Signal Process 30, 1521–1548 (2011). https://doi.org/10.1007/s00034-011-9310-0

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  • DOI: https://doi.org/10.1007/s00034-011-9310-0

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