Abstract
In this paper, a low voltage and ultra low power operational transconductance amplifier (OTA) is presented. As will be shown, the transient response and open loop gain of the proposed OTA are improved using adaptive biasing and DC gain enhancement techniques. The contributions of the proposed OTA are ultra low power consumption (only 3.977 μw), low supply voltages (±0.6 V), high swing, high speed, and high gain. It can clearly be seen that for the proposed OTA, the gain of the differential half-circuit in the input stage (A d ), DC gain (A 0), gain bandwidth (GBW), and slew rate (SR) are increased, whereas the settling time (T S ) is decreased. The results of simulations done using 0.18 μm Silterra CMOS process technology and the measurement results are presented to validate and compare the advantages of this work and other related works.
Similar content being viewed by others
References
D.J. Allstot, A precision variable-supply CMOS comparator. IEEE J. Solid-State Circuits 9, 1080–1087 (1982)
T.V. Cao, D.T. Wisland, T.S. Lande, F. Moradi, Rail-to-rail low-power fully differential OTA utilizing adaptive biasing and partial feedback, in Proc. IEEE Int. Symp. Cir. and Sys. (2010), pp. 2820–2823
T.V. Cao, D.T. Wisland, T.S. Lande, A. Moradi, Low-power, enhanced-gain adaptive-biasing-based operational transconductance amplifiers, in Proc. IEEE NORCHIP Conf. (2009), pp. 1–4
M.G. Degrauwe, J. Rijmenants, E.A. Vittoz, H. DeMan, Adaptive biasing CMOS amplifiers. IEEE J. Solid-State Circuits 17, 522–528 (1982)
G. Ferri, V. Stornelli, A. Celeste, Integrated rail-to-rail low-voltage low-power enhanced DC-gain fully differential OTA. ETRI J. 29(6), 785–793 (2007)
H.B. Gabbouj, N. Hassen, K. Besbes, Low voltage gain linear class AB CMOS OTA with DC level input stage. Int. J. Electr. Electron. Eng. 5(4), 235–241 (2011)
H.Y. Huang, B.R. Wang, J.C. Liu, High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit, in Proc. IEEE Int. Symp. Cir. and Sys. (2006), pp. 906–910
N. Jayakumar, S. Paul, R. Garg, K. Gulati, S.P. Hatri, Minimizing and Exploiting Leakage in VLSI Design (Springer, New York, 2010)
A.R. Kim, H.R. Kim, Y. Park, Y.K. Choi, B.S. Kong, Low-power class-AB CMOS OTA with high slew rate, in Proc. Int. SOC Design Conf. (ISOCC) (2009), pp. 313–316
R. Laker, W.M. Sansen, Design of Analog Integrated Circuits and Systems (McGraw-Hill, New York, 1994)
C. Lin, M. Ismail, A low-voltage CMOS rail-to-rail class AB input-output op-amp with slew rate and settling enhancement, in Proc. ISCAS, vol. 98 (1998), pp. 132–136
A.J. López-Martín, S. Baswa, J. Ramirez-Angulo, Low-voltage power-efficient adaptive biasing for CMOS amplifiers and buffers. Electron. Lett. 40(4), 217–219 (2004)
A.P. Perez, K.Y.B. Nithin, E. Bonizzoni, F. Maloberti, Slew rate and gain enhancement in two stage operational amplifiers, in Proc. IEEE Int. Symp. Cir. and Sys. (2009), pp. 24–27
M.A.T. Sanduleanu, E.A.J.R.V. Tuijl, Power Trade-offs and Low Power in Analog CMOS ICs (Kluwer Academic, Boston, 2002)
E. Vittoz, J. Felirath, CMOS analog integrated circuits based on weak inversion operation. IEEE J. Solid-State Circuits 12(3), 33–37 (1977)
A. Wang, B.H. Calhoun, A.P. Chandrakasan, Sub-threshold Design for Ultra Low-Power Systems (Springer, New York, 2006)
Acknowledgement
This paper is the result of a research project supported by Kharazmi University.
Author information
Authors and Affiliations
Corresponding author
Additional information
H. Fathabadi is also currently a Post-Doctoral researcher at National Technical University of Athens, Greece.
Rights and permissions
About this article
Cite this article
Fathabadi, H. Ultra Low Power Improved Differential Amplifier. Circuits Syst Signal Process 32, 861–875 (2013). https://doi.org/10.1007/s00034-012-9475-1
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-012-9475-1