Abstract
Given the popularity of decimal arithmetic, hardware implementation of decimal operations has been a hot topic of research in recent decades. Besides the four basic operations, the square root can be implemented as an instruction directly in the hardware, which improves the performance of the decimal floating-point unit in the processors. Hardware implementation of decimal square rooters is usually done using either functional or digit-recurrence algorithms. Functional algorithms, entailing multiplication per iteration, seem inadequate to use for decimal square roots, given the high cost of decimal multipliers. On the other hand, digit-recurrence square root algorithms, particularly SRT (this method is named after its creators, Sweeney, Robertson, and Tocher) algorithms, are simple and well suited for decimal arithmetic. This paper, with the intention of reducing the latency of the decimal square root operation while maintaining a reasonable cost, proposes an SRT algorithm and the corresponding hardware architecture to compute the decimal square root. The proposed fixed-point square root design requires n+3 cycles to compute an n-digit root; the synthesis results show an area cost of about 31K NAND2 and a cycle time of 40 FO4. These results reveal the 14 % speed advantage of the proposed decimal square root architecture over the fastest previous work (which uses a functional algorithm) with about a quarter of the area.
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Notes
ulp means unit in least (significant) position.
The upper bound of X with q 0=0 is \(( 0.55 \ldots ) ^{2} = ( \frac{5}{9} ) ^{2} = \frac{25}{81} \approx0.3\).
Fan-out of 4, i.e., the latency of an inverter driving 4 similar inverters in the output.
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Acknowledgements
This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC). The authors would like to express their appreciation for the comments of the anonymous reviewers for improving this paper.
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Kaivani, A., Ko, SB. Decimal SRT Square Root: Algorithm and Architecture. Circuits Syst Signal Process 32, 2137–2150 (2013). https://doi.org/10.1007/s00034-013-9586-3
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DOI: https://doi.org/10.1007/s00034-013-9586-3