Abstract
A simplified DFT-based algorithm and its VLSI implementation for accurate frequency estimation of single-tone complex sinusoid signal are investigated. The proposed algorithm estimates frequency by interpolation using Fourier coefficients. It consists of a coarse search followed by a fine search, and its performance closely achieves the Cramer–Rao low bound (CRLB) even in low SNR region. Moreover, a pipelined triple-mode CORDIC architecture is designed to efficiently support complex multiplication, complex magnitude calculation and real division. The triple-mode CORDIC-based radix-4 architecture is employed for the hardware implementation of the frequency estimator, and is suitable for not only fast Fourier transformation but also accurate frequency estimation. A frequency estimator with 1024-point samples is implemented and verified on FPGA. It works at 215 MHz on a Xilinx XC6VLX240T FPGA device, and uses up 4,161 registers and 6,986 slice LUTs. ASIC synthesis results show that it requires an area of 60K equivalent NAND2 gates with a clock rate of 500 MHz at SMIC 0.18 μm technology. The whole latency of the frequency estimator is 2336 cycles. The proposed architecture provides a good trade off between hardware overhead, estimation performance and computation latency.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
E. Aboutanios, B. Mulgrew, Iterative frequency estimation by interpolation on Fourier coefficients. IEEE Trans. Signal Process. 53(4), 1237–1242 (2005)
A. Banerjee, A.S. Dhar, Pipelined VLSI architecture using CORDIC for transform domain equalizer. J. Signal Process. Syst. 70, 39–48 (2013)
C. Candan, A method for fine resolution frequency estimation from three DFT samples. IEEE Signal Process. Lett.. 18(6), 351–354 (2011)
H. Fu, P.Y. Kam, MAP/ML estimation of the frequency and phase of single sinusoid in noise. IEEE Trans. Signal Process. 55(3), 834–845 (2007)
W. Hussain, F. Garzia, Designing fast Fourier transform accelerators for orthogonal frequency-division multiplexing systems. J. Signal Process. Syst. 69, 161–171 (2012)
E. Jacobsen, P. Kootsookos, Fast, accurate frequency estimator. IEEE Signal Process. Mag. 24(3), 123–125 (2007)
Y. Liu, Z. Nie, Z. Zhao, An iterative frequency estimation algorithm using generalized Fourier interpolation. Chin. J. Electron. 18(3), 564–568 (2009)
Y. Liu, Z. Nie, Z. Zhao, Q.H. Liu, Generalization of iterative Fourier interpolation algorithms for single frequency estimation. Digit. Signal Process. 21, 141–149 (2011)
D. Liu, H. Liu, J. Zhang, B. Zhang, L. Zhou, VLSI design of a hardware efficient FFT processor, in Proceeding of Future Information Technology, Application, and Service (2012), pp. 61–70
U. Mengali, A.N. Andrea, Synchronization Techniques for Digital Receivers (Plenum Press, New York, 1997)
G. Michael, R. Burghard, C. Reiner, Memory Architecture and Parallel Access (Elsevier, New York, 1994)
P.K. Meher, J. Valls, T.B. Juang, K. Sridharan, K. Maharatna, 50 Years of CORDIC: algorithm, architectures and applications. IEEE Trans. Circuits Syst. I, Regul. Pap. 56(9), 1893–1907 (2009)
P.K. Meher, S.Y. Park, CORDIC designs for fixed angle of rotation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(2), 217–228 (2013)
T.O. Pitkanen, J. Takala, Low-power application-specific processor for FFT computations. J. Signal Process. Syst. 63, 165–176 (2011)
S.Y. Park, Y.J. Yu, Fixed-point analysis and parameter selections of MSR-CORDIC with applications to FFT designs. IEEE Trans. Signal Process. 60(2), 6245–6255 (2012)
B.G. Quinn, Estimating frequency by interpolation using Fourier coefficients. IEEE Trans. Signal Process. 42(2), 1264–1268 (1994)
D.C. Rife, R.R. Boorstyn, Single-tone parameter estimation from discrete-time observation. IEEE Trans. Inf. Theory IT-20(5), 591–598 (1974)
T.Y. Sung, H.C. Hsin, Y.P. Cheng, Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems. Digit. Signal Process. 20(2), 511–527 (2010)
J.H. Takalala, T.S. Jarvinen, H.T. Sorokin, Conflict-free parallel memory access scheme for FFT processors, in Proceeding of IEEE International Symposium on Circuits and Systems (2003), pp. 524–527
L. Vachhani, K. Sridharan, P.K. Meher, Efficient CORDIC algorithm and architectures for low area and high throughput implementation. IEEE Trans. Circuits Syst. II, Express Briefs 21(2), 61–65 (2009)
J.E. Volder, The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput. 20, 330–334 (1959)
J.S. Walther, A unified algorithm for elementary function, in Proceeding of Joint Spring Computer Conference (1971), pp. 379–385
D. Wang, P. Ren, L. Liu, A high-throughput fixed-point complex divider for FPGAs. IEICE Electron. Express 10(4), 1–8 (2013)
H. Xiao, A. Pan, Y. Chan, X. Zeng, Low-cost reconfigurable VLSI architecture for fast Fourier transform. IEEE Trans. Consum. Electron. 54(4), 1617–1622 (2008)
Acknowledgements
The authors would like to thank the editors and anonymous reviewers for providing valuable comments which helped in improving the manuscript. This work is supported by the National Natural Science Foundation of China, under Grant No. 60970037.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Liu, D., Liu, H., Zhou, L. et al. Computationally Efficient Architecture for Accurate Frequency Estimation with Fourier Interpolation. Circuits Syst Signal Process 33, 781–797 (2014). https://doi.org/10.1007/s00034-013-9660-x
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-013-9660-x