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A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures

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Abstract

Finite impulse response (FIR) filtering is a ubiquitous operation in digital signal processing systems and is generally implemented in full custom circuits due to high-speed and low-power design requirements. The complexity of an FIR filter is dominated by the multiplication of a large number of filter coefficients by the filter input or its time-shifted versions. Over the years, many high-level synthesis algorithms and filter architectures have been introduced in order to design FIR filters efficiently. This article reviews how constant multiplications can be designed using shifts and adders/subtractors that are maximally shared through a high-level synthesis algorithm based on some optimization criteria. It also presents different forms of FIR filters, namely, direct, transposed, and hybrid and shows how constant multiplications in each filter form can be realized under a shift-adds architecture. More importantly, it explores the impact of the multiplierless realization of each filter form on area, delay, and power dissipation of both custom (ASIC) and reconfigurable (FPGA) circuits by carrying out experiments with different bitwidths of filter input, design libraries, reconfigurable target devices, and optimization criteria in high-level synthesis algorithms.

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Notes

  1. An integer can be written in CSD using \(n\) digits as \(\sum _{i=0}^{n-1} d_i 2^{i}\), where \(d_i \in \{1, 0, \overline{1}\}\) and \(\overline{1}\) denotes \(-1\). The nonzero digits are not adjacent, and a constant is represented with minimum number of nonzero digits under CSD.

  2. MSD differs from CSD in one property which allows the nonzero digits to be adjacent. Thus, a constant may have alternative representations in MSD, all including minimum number of nonzero digits.

  3. The top signal path carrying the delayed filter input in Fig. 1a.

  4. The bottom signal path including the adders that compute the filter output in Fig. 1a.

  5. The adder that computes the filter output is always assumed to be connected to a register even this register is not synthesized in hardware.

  6. The bitwidth of the filter output is computed as \(bwi + \lceil log_2\sum _{i=0}^{N-1}|h_i|\rceil \), where \(h_i\) is the \(i\mathrm{th}\) fixed-point filter coefficient with \(0 \le i \le N-1\).

  7. The design library is available at www.nangate.com.

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Acknowledgments

This work was supported by the national funds through FCT, Fundação para a Ciência e a Tecnologia, under Project PEst-OE/EEI/LA0021/2013.

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Authors and Affiliations

  1. INESC-ID, Lisbon, Portugal

    Levent Aksoy

  2. INESC-ID/Tecnico ULisboa, Lisbon, Portugal

    Paulo Flores & José Monteiro

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  1. Levent Aksoy
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Correspondence to Levent Aksoy.

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Aksoy, L., Flores, P. & Monteiro, J. A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. Circuits Syst Signal Process 33, 1689–1719 (2014). https://doi.org/10.1007/s00034-013-9727-8

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