A Low-Memory-Access Length-Adaptive Architecture for 2$^n$-Point FFT

Abstract

Fast Fourier transformation (FFT) is widely used in modern wireless communication and digital signal processing. Because memory access is a major cause of power dissipated by the long-length FFT architecture, this paper explores the design space expanded by FFT size and radix number in detail and presents a novel low-memory-access length-adaptive architecture for computing any long-length 2$^n$-point FFT. The proposed hardware solution possesses the following three attractive features to reflect its novelty as compared to the existing designs. First, the authors identified that memory consumes major energy dissipation of a FFT processor and proposed to reduce memory access through decreasing the number of FFT butterfly stages. The second one is that we adopt the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware for computing variable-length FFT without sacrificing the hardware utilization as contrary to the feed-forward architecture. Finally, a 16-bank memory organization is proposed to achieve conflict-free FFT operations for various radixes. Such low-memory-access length-adaptive architecture can reduce almost 70 % memory access or 30 % power consumption for FFT computation. After being implemented through 1P6M TSMC 0.18-$\upmu$m CMOS technology, this work costs a core area of only 4.49 mm$^{2}$ and meets the FFT real-time performance requirements of DVB-T2 systems when operated at 20 MHz frequency. The proposed design consumes only 1.44 nJ of energy per sample for computing FFTs. Through adopting the proposed low-memory-access algorithm, flexible length-adaptive architecture, and efficient 16-bank memory organization, 56 % power dissipation of the whole FFT chip can be saved.

Appendix: Fetching Data for Radix-2, Radix-4, and Radix-8 FFTs

Addressing modes are given for fetching data from the memory into the data-path for FFT operation based on radix-2, radix-4, and radix-8, respectively. The first one is for computing radix-2 FFT in which $x(n)$ are fetched from the following address Addr[$x(n)$] inside the memory bank Bank[$x(n)$] of memory to the FFT data-path.

$$\begin{aligned}&{\text {Addr}}\left[ {x( n)} \right] =( {\# {\text {cycle}}}) \hbox {mod } ({N/16}) \end{aligned}$$

(22)

$$\begin{aligned}&{\text {Banks}}\left[ {x( n)} \right] =\,\,\,\left\lfloor {\frac{\# {\text {cycle}}}{N/16}} \right\rfloor \quad {\text {and}} \quad \left\lfloor {\frac{\# {\text {cycle}}}{N/16}} \right\rfloor \,+\,8 \end{aligned}$$

(23)

Besides, the partial timing diagram is shown as Fig. 11. From the figure, we can find that the numbers of a pair of banks are kept unchanged for 512 cycles, and the address number increments every clock cycle. After all the data of the two acting banks are fetched, the bank numbers increment to continue fetching data from the next pair of banks.

Fig. 11

The timing diagram of data fetching for FFT operation based on radix-2 algorithm

The second one is for computing radix-4 FFT where $x(n)$ are fetched from the following locations of memory to the FFT data-path for computing.

$$\begin{aligned} {\text {Addr}}\left[ {x( n)} \right]&=\,\,\,\left\lfloor {\frac{(\# {\text {cycle}}) \, \mathrm{{mod}} \, (N/16)}{2}} \right\rfloor \end{aligned}$$

(24)

$$\begin{aligned} {\text {Banks}}\left[ {x( n)} \right]&=\,\left\lfloor {\frac{\# {\text {cycle}}}{N/8}} \right\rfloor \cdot {\overline{(\# {\text {cycle}}) \, {\text {mod}} \, (2),}} \left( \left\lfloor {\frac{\# {\text {cycle}}}{N/8}} \right\rfloor \,+\;8\right) \nonumber \\&\quad \cdot \,{\overline{(\# {\text {cycle}}){\text {mod}} \,(2),}}\left( \left\lfloor {\frac{\# {\text {cycle}}}{N/8}} \right\rfloor \,+\;4\right) \cdot \left[ ( {\# {\text {cycle}}}){\text {mod}} \, (2)\right] ,\nonumber \\&\quad \left( \left\lfloor {\frac{\# {\text {cycle}}}{N/8}} \right\rfloor \,+\;12\right) \cdot \,[\,( {\# {\text {cycle}}}){\text {mod}} \, (2)] \end{aligned}$$

(25)

The partial timing diagram of data fetching for FFT operation based on radix-4 algorithm is shown as Fig. 12. From the figure, we can find that two pairs of banks form a basic unit and the data inside are fetched in order during 1,024 cycles. Thus, the address number increments every two clock cycles. After all the data of the acting unit are fetched, the bank numbers increment to continue fetching data from the next unit.

Fig. 12

The timing diagram of data fetching for FFT operation based on radix-4 algorithm

Furthermore, for calculating radix-8 FFT, $x(n)$ are fetched from the locations of memory as shown in Fig. 13 to the FFT data-path for computing. From the figure, we can find that four pairs of banks form a basic unit and the data inside are fetched in order during 2,048 cycles. Thus, the address number increments every four clock cycles. After all the data of the acting unit are fetched, the bank numbers increment to continue fetching data from the next unit.

Fig. 13

The timing diagram of data fetching for FFT operation based on radix-8 algorithm