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Phase Interpolator with Improved Linearity

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Abstract

An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required.

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Authors and Affiliations

  1. Department of Physics, University of Patras, Patras, Greece

    George Souliotis & Costas Laoudias

  2. Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece

    Fotis Plessas

  3. Department of Computing and Communication Technologies, Faculty of Technology, Design and Environment, Oxford Brookes University, Wheatley, Oxford, UK

    Nikolaos Terzopoulos

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  1. George Souliotis
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  2. Costas Laoudias
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  3. Fotis Plessas
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  4. Nikolaos Terzopoulos
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Correspondence to George Souliotis.

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Souliotis, G., Laoudias, C., Plessas, F. et al. Phase Interpolator with Improved Linearity. Circuits Syst Signal Process 35, 367–383 (2016). https://doi.org/10.1007/s00034-015-0082-9

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  • DOI: https://doi.org/10.1007/s00034-015-0082-9

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