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A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs

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Abstract

Using multiple-valued logic provides more information transmission over a signal line. So it could solve the binary logic circuits problems such as interconnections requirement. In this paper, a universal method for designing ternary 3-2 and 4-2 compressor cells based on carbon nanotube field-effect transistors (CNTFETs) is presented. The proposed circuits use unique properties of CNTFETs, such as adjustable threshold voltage by changing CNT diameter and ballistic carrier transportation. In both designs transmission gates, ternary decoder and standard ternary buffers with different threshold voltages are used. The proposed compressors receive three (for 3-2 compressor) or four (for 4-2 compressor) ternary digits, produce the summation of these digits and show the results in two ternary digits (Sum, Carry). For evaluation and simulation the proposed circuits, Synopsys HSPICE simulator with 32 nm compact model is used in different simulation conditions.

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References

  1. A. Abu El-Seoud, M. El-Banna, M. Hakim, On modelling and characterization of single electron transistor. Int. J. Electron. 94, 573–585 (2007)

    Article  Google Scholar 

  2. E. Alkaldy, K. Navi, F. Sharifi, M.H. Moaiyeri, An ultra high-speed (4; 2) compressor with a new design approach for nanotechnology based on the multi-input majority function. J. Comput. Theor. Nanosci. 11, 1691–1696 (2014)

    Article  Google Scholar 

  3. S. Angizi, S. Sarmadi, S. Sayedsalehi, K. Navi, Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata. Microelectron. J. 46, 43–51 (2015)

    Article  Google Scholar 

  4. P.C. Balla, A. Antoniou, Low power dissipation MOS ternary logic family. IEEE J. Solid-State Circuits 19, 739–749 (1984)

    Article  Google Scholar 

  5. G. Cho, Y.-B. Kim, F. Lombardi, M. Choi, Performance evaluation of CNFET-based logic gates. In Instrumentation and Measurement Technology Conference, 2009. I2MTC’09. IEEE (IEEE, 2009), pp. 909–912

  6. J. Deng, Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors (Stanford University, Stanford, 2007)

    Google Scholar 

  7. J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region. IEEE Trans. Electron Dev. 54, 3186–3194 (2007)

    Article  Google Scholar 

  8. J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Dev. 54, 3195–3205 (2007)

    Article  Google Scholar 

  9. S.L. Hurst, Multiple-valued logic&# 8212; its status and its future. IEEE Trans. Comput. 100, 1160–1179 (1984)

    Article  Google Scholar 

  10. Y.-B. Kim, Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans. Electr. Electron. Mater. 11, 93–105 (2010)

    Article  Google Scholar 

  11. S. Lin, Y.-B. Kim, F. Lombardi, A novel CNTFET-based ternary logic gate design. In 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009. MWSCAS’09 (IEEE, 2009), pp. 435–438

  12. S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10, 217–225 (2011)

    Article  Google Scholar 

  13. P.L. Mceuen, M.S. Fuhrer, H. Park, Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1, 78–85 (2002)

    Article  Google Scholar 

  14. M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Dev. Syst. 5, 285–296 (2011)

    Article  MATH  Google Scholar 

  15. M.H. Moaiyeri, R.F. Mirzaee, A. Doostaregan, K. Navi, O. Hashemipour, A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. IET Comput. Digit. Tech. 7, 167–181 (2013)

    Article  Google Scholar 

  16. M.H. Moaiyeri, R.F. Mirzaee, K. Navi, O. Hashemipour, Efficient CNTFET-based ternary full adder cells for nanoelectronics. Nano-Micro Lett. 3, 43–50 (2011)

    Article  Google Scholar 

  17. A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4, 168–179 (2005)

    Article  Google Scholar 

  18. A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54, 2391–2401 (2007)

    Article  Google Scholar 

  19. K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91, 305–327 (2003)

    Article  Google Scholar 

  20. X. Wu, F. Prosser, CMOS ternary logic circuits. IEE Proc. G (Circuits Dev. Syst.) 137, 21–27 (1990)

    Article  Google Scholar 

  21. Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, A. Yoshida, Realization of quaternary logic circuits by n-channel MOS devices. IEEE J. Solid-State Circuits 21, 162–168 (1986)

    Article  Google Scholar 

Download references

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran

    Sepehr Tabrizchi

  2. Department of Computer Engineering, Vali-e-Asr University of Rafsanjan, P.O. Box 518, Rafsanjan, Iran

    Hojjat Sharifi

  3. Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, G.C., Tehran, Iran

    Fazel Sharifi & Keivan Navi

Authors
  1. Sepehr Tabrizchi
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  2. Hojjat Sharifi
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  3. Fazel Sharifi
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  4. Keivan Navi
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Correspondence to Keivan Navi.

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Tabrizchi, S., Sharifi, H., Sharifi, F. et al. A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs. Circuits Syst Signal Process 35, 3310–3322 (2016). https://doi.org/10.1007/s00034-015-0197-z

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  • DOI: https://doi.org/10.1007/s00034-015-0197-z

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