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An 8-bit, 10 KS/s, \(1.87\upmu \text {W}\) Successive Approximation Analog to Digital Converter in \(0.25\,\upmu \hbox {m}\) CMOS Technology for ECG Detection Systems

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Abstract

This paper presents an 8-bit successive approximation analog to digital converter (SA-ADC) employing a mostly digital implementation for portable Electrocardiogram (ECG) detection systems. At 10 K samples/s, the proposed SA-ADC consumes \(1.87\,\upmu \hbox {W}\) from a 1 V power supply. The layout and extraction of the proposed SA-ADC are done using L-edit and simulated using TSMC \(0.25\,\upmu \hbox {m}\) technology file on Pspice. According to the simulation results, the SA-ADC has a signal-to-noise ratio of 57 dB, peak spurious-free dynamic range of 41 dB, and a signal-to-noise-and-distortion ratio of 40.5 dB for a 200 Hz–\(500\hbox {mV}_{\mathrm{pp}}\) input sine wave. In addition to that, the SA-ADC has effective number of bits of 6.5-bits, an effective resolution bandwidth of 1.5 kHz and a figure of merit of 6.85 pJ/Conversion step. The digitized ECG signal is precisely reconstructed using a novel reconstruction circuit. These results show that the proposed SA-ADC in \(0.25\,\upmu \hbox {m}\) technology is a good candidate for ECG detection systems.

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Acknowledgments

The authors highly appreciate the valuable comments of the reviewers and the revisions of Prof. Ahmed Elwakil and Dr. Mohamed Saad.

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Authors and Affiliations

  1. Electrical and Computer Engineering Department, Sharjah University, Sharjah, UAE

    Soliman A. Mahmoud, Heba A. Salem & Hend M. Albalooshi

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  1. Soliman A. Mahmoud
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  2. Heba A. Salem
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  3. Hend M. Albalooshi
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Correspondence to Soliman A. Mahmoud.

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Mahmoud, S.A., Salem, H.A. & Albalooshi, H.M. An 8-bit, 10 KS/s, \(1.87\upmu \text {W}\) Successive Approximation Analog to Digital Converter in \(0.25\,\upmu \hbox {m}\) CMOS Technology for ECG Detection Systems. Circuits Syst Signal Process 34, 2419–2439 (2015). https://doi.org/10.1007/s00034-015-9973-z

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