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Approximate Arithmetic for Low-Power Image Median Filtering

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Abstract

In applications related to human senses, such as audio and image processing, computations with limited precision are acceptable. In these areas, a digital system can be implemented using approximate computing that works with sufficient precision. In this paper, we present a method to design 2-bit approximate magnitude comparators that are effectively low cost in terms of power, area and speed. We build larger comparators with adjustable error characteristics. Compared to precise one, our approximate comparators can save power and area up to 7–46 % and 10–50 %, respectively. The structures of our comparators and their error characteristics are presented in this paper. We use these comparators to design different approximate image median filters in order to remove salt and pepper noise. Simulation results show that the output quality of these filters is very similar to that of the precise ones so that the degradation is not noticeable. The approximate filters save up to 30 % of power and area while working 18 % faster than the precise ones.

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References

  1. S. Abdel-Hafeez, A. Gordon-Ross, B. Parhami, Scalable digital CMOS comparator using a parallel prefix tree. IEEE Trans. Very Large Scale Integr. Syst. 21(11), 1989–1998 (2013)

  2. D. Alnajiar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye, Coarse-grained dynamically reconfigurable architecture with flexible reliability, in IEEE International Conference on Field Programmable Logic and Applications (FPL’09), pp. 186–192 (2009)

  3. L. Budin, D. Jakobović, M. Golub, Genetic algorithms in real-time imprecise computing. J. Comput. Inf. Technol. 8(3), 249–257 (2004)

    Google Scholar 

  4. C. Chakrabarti, Sorting network based architectures for median filters. IEEE Trans. Circuit Syst. II Analog Digit. Signal Process. 40(11), 723–727 (1993)

    Article  Google Scholar 

  5. L.N. Chakrapani, B.E.S. Akgul, S. Cheemalavagu, P. Korkmaz, K.V. Palem, B. Seshasayee, Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology, in Design, Automation and Test in Europe (DATE ’06), 6–10 March, pp. 1–6 (2006)

  6. S. Cheemalavagu, P. Korkmaz, K.V. Palem, B.E.S. Akgul, L.N. Chakrapani, A probabilistic CMOS switch and its realization by exploiting noise, in IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 535–541 (2005)

  7. X. Cheng, M.S. Hsiao, Region-level approximate computation reuse for power reduction in multimedia applications, in ACM International Symposium on Low Power Electronics and Design (ISLPED ’05), pp. 119–122 (2005)

  8. H. Chishiro, A. Takeda, K. Funaoka, N. Yamasaki, Semi-fixed-priority scheduling: new priority assignment policy for practical imprecise computation, in IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 23–25 August, pp. 339–348 (2010)

  9. L. Christopher, W. Mayweather III, S. Perlman, A VLSI median filter for impulse noise elimination in composite or component TV signals. IEEE Trans. Consum. Electron. 34(1), 262–267 (1988)

    Article  Google Scholar 

  10. J. Epps, Fast approximate computation of non-uniform DFTs for biological sequence analysis. Electron. Lett. 45(8), 429–430 (2009)

    Article  Google Scholar 

  11. D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N.S. Kim, K. Flautner, Razor: circuit-level correction of timing errors for low-power operation. IEEE Micro 24(6), 10–20 (2004)

    Article  Google Scholar 

  12. F. Firouzi, A. Azarpeyvand, M.E. Salehi, S.M. Fakhraie, Adaptive fault-tolerant DVFS with dynamic online AVF prediction. Microelectron. Reliab. 52(6), 1197–1208 (2012)

    Article  Google Scholar 

  13. J. George, B. Marr, B. Akgul, K. Palem, Probabilistic arithmetic and energy efficient embedded signal processing, in IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 158–168 (2006)

  14. R. Gonzalez, P. Wintz, Digital Image Processing (Addison-Waley, Reading, 1987)

    Google Scholar 

  15. A. Gupta, S. Mandavalli, V.J. Mooney, L. Keck-Voon, A. Basu, H. Johan, B. Tandianus, Low power probabilistic floating point multiplier design, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI’11), 4–6 July, pp. 182–187 (2011)

  16. V. Gupta, D. Mohapatra, S.P. Park, A. Raghunathan, K. Roy, IMPACT: IMPrecise adders for low-power approximate computing, in International Symposium on Low Power Electronics and Design (ISLPED’11), 1–3 August, pp. 409–414 (2011)

  17. V. Gupta, D. Mohapatra, A. Raghunathan, K. Roy, Low-power digital signal processing using approximate adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1), 124–137 (2013)

    Article  Google Scholar 

  18. J. Han, M. Orshansky, Approximate computing: an emerging paradigm for energy-efficient design, in 18th IEEE EuropeanTest Symposium (ETS), pp. 1–6 (2013)

  19. B. Heck Ferri, N. Perrin, A. Ferri, Adaptive length IIR filters implemented with imprecise computing, in American Control Conference (ACC ’07), 9–13 July, pp. 2887–2892 (2007)

  20. L. Hing-Mo, T. Chi-Ying, A MUX-based high-performance single-cycle CMOS comparator. IEEE Trans. Circuits Syst. II Express Briefs 54(7), 591–595 (2007). doi:10.1109/TCSII.2007.899856

    Article  Google Scholar 

  21. H. Jiawei, J. Lach, Exploring the fidelity-efficiency design space using imprecise arithmetic, in 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25–28 January, pp. 579–584 (2011)

  22. V. Jimenez-Fernandez, D. Martinez-Navarrete, C. Ventura-Arizmendi, Z. Hernandez-Paxtian, J. Ramirez-Rodriguez, Digital circuit architecture for a median filter of grayscale images based on sorting network. Int. J. Circuits Syst. Signal Process. 5(3), 297–304 (2011)

    Google Scholar 

  23. J. Juhola, P. Haavisto, O. Vainio, T. Raita-aho, Y. Neuvo, On VLSI implementation of median based field rate up-conversion, in IEEE International Symposium on Circuits and Systems, 1–3 May, pp. 3042–3045 (1990)

  24. Z. Kedem, V. Mooney, K. Krishna, Muntimadugu, A. Devarasetty, P.D. Parasuramuni, optimizing energy to minimize errors in dataflow graphs using approximate adders. Paper Presented at the International 11th Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Arizona, USA (2010)

  25. Z.M. Kedem, V.J. Mooney, K.K. Muntimadugu, K.V. Palem, an approach to energy-error tradeoffs in approximate ripple carry adders, in International Symposium on Low Power Electronics and Design (ISLPED’11), 1–3 August, pp. 211–216 (2011)

  26. Z.M. Kedem, V.J. Mooney, K.K. Muntimadugu, K.V. Palem, An approach to energy-error tradeoffs in approximate ripple carry adders, in 2011 International Symposium on Low Power Electronics and Design (ISLPED) 1–3 August, pp. 211–216 (2011)

  27. M. Kim, J.-Y. Kim, H.-J. Yoo, A 1.55 ns 0.015 mm 2 64-bit quad number comparator, in IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’09), pp. 283–286 (2009)

  28. T. Le, M. Glesner, A flexible and approximate computing approach for time–frequency distributions. IEEE Trans. Signal Process. 48(4), 1193–1196 (2000)

    Article  MathSciNet  MATH  Google Scholar 

  29. C.L. Lee, C.-W. Jen, Bit-sliced median filter design based on majority gate. IEEE Proc. G Circuits Devices Syst. 139(1), 63–71 (1992)

    Article  Google Scholar 

  30. T.-W. Lee, J.-H. Lee, S.-B. Cho, FPGA Implementation of a 3/spl times/3 window median filter based on a new efficient bit-serial sorting algorithm. in IEEE 7th Korea–Russia International Symposium on Science and Technology, pp. 237–242 (2003)

  31. K. Lengwehasatit, A. Ortega, DCT computation based on variable complexity fast approximations. in International Conference on Image Processing (ICIP 98), October 4–7, pp. 95–99 (1998)

  32. T. Li-Ping, C. Jia-Ming, H. Wei-Fen, S. Wei-Kuan, An imprecise computation model in reducing power consumption of flash memory for portable devices, in 28th Annual International Computer Software and Applications Conference (COMPSAC’04), 28–30 September, pp. 62–63 (2004)

  33. C.C. Lin, C.J. Kuo, Two-dimensional rank-order filter by using max-min sorting network. IEEE Trans. Circuits Syst. Video Technol. 8(8), 941–946 (1998)

    Article  Google Scholar 

  34. J.W.S. Liu, S. Wei-Kuan, L. Kwei-Jay, R. Bettati, C. Jen-Yao, Imprecise computations. IEEE Spec. Issue Real-Time Syst. 82(1), 83–94 (1994)

    Google Scholar 

  35. C. Long-Wen, J.H. Lin, A bit-level systolic array for median filter. IEEE Trans. Signal Process. 40(8), 2079–2083 (1992)

    Article  Google Scholar 

  36. H.R. Mahdiani, A. Ahmadi, S.M. Fakhraie, C. Lucas, Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans. Circuits Syst. 57(4), 850–862 (2010)

    Article  MathSciNet  Google Scholar 

  37. H.R. Mahdiani, S.M. Fakhraie, C. Lucas, Relaxed fault-tolerant hardware implementation of neural networks in the presence of multiple transient errors. IEEE Trans. Neural Netw. Learn. Syst. 23(8), 1215–1228 (2012)

    Article  Google Scholar 

  38. T. Matsubara, V.G. Moshnyaga, K. Hashimoto, A low-complexity and low power design of 2D-median filter. ECTI Trans. Comput. Eng. Comput. Inf. Technol. 5(2), 1–9 (2011)

    Google Scholar 

  39. D. Mohapatra, V.K. Chippa, A. Raghunathan, K. Roy, Design of voltage-scalable meta-functions for approximate computing, in Design, Automation & Test in Europe Conference and Exhibition (DATE), 14–18 March, pp. 1–6 (2011)

  40. B. Morcego, J. Frau, A. Català, Suavizado de Imágenes en Tiempo Real mediante Filtrado por Mediana Utilizando Arrays Sistólicos, in VII Conference on Design of Circuits and Integrated Systems (DCIS), pp. 545–546 (1992)

  41. V.G. Moshnyaga, K. Hashimoto, An efficient implementation of 1-D median filter, in IEEE 52nd International Midwest Symposium on Circuits and Systems (MWSCAS’09), pp. 451–454 (2009)

  42. Z. Ning, G. Wang Ling, Y. Kiat Seng, An enhanced low-power high-speed adder for error-tolerant application, in 12th International Symposium on Integrated Circuits (ISIC ’09), 14–16 December, pp. 69–72 (2009)

  43. Z. Ning, G. Wang Ling, W. Gang, Y. Kiat Seng, Enhanced low-power high-speed adder for error-tolerant application, in International SoC Design Conference (ISOCC’10), 22–23 November, pp. 323–327 (2010)

  44. Z. Ning, G. Wang Ling, Z. Weija, Y. Kiat Seng, K. Zhi Hui, Design of low-power high-speed truncation-error-tolerant added and its application in digital signal processing. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(8), 1225–1229 (2010)

    Article  Google Scholar 

  45. Z. Ning, G. Wang Ling, Y. Kiat Seng, Ultra low-power high-speed flexible probabilistic adder for error-tolerant applications, in International SoC Design Conference (ISOCC’11), 17–18 November, pp. 393–396 (2011)

  46. S. Nocco, S. Quer, A probabilistic and approximated approach to circuit-based formal verification. J. Satisfiabil. Boolean Model. Comput. 5, 111–132 (2008)

    MathSciNet  Google Scholar 

  47. J. Nousiainen, J. Isoaho, O. Vainio, Fast implementation of stack filters with VHDL-based synthesis and FPGAs, in IEEE Winter Workshop on Nonlinear Digital Signal Processing, pp. 5.2–5. 6 (1993)

  48. K. Oflazer, Design and implementation of a single-chip 1-D median filter. IEEE Trans. Acoust. Speech Signal Process. 31(5), 1164–1168 (1983)

    Article  Google Scholar 

  49. K. Oflazer, Design and implementation of a single-chip 1-D median filter. IEEE Trans. Acoust. Speech Signal Process. 31(5), 1164–1168 (1983). doi:10.1109/tassp.1983.1164203

    Article  Google Scholar 

  50. Y. Pang, K. Radecka, An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking, in 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 15–18 May, pp. 1736–1739 (2011)

  51. Y. Pang, K. Radecka, An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking, in IEEE International Symposium on Circuits and Systems (ISCAS’11), 15–18 May, pp. 1736–1739 (2011)

  52. J.C. Russ, The Image Processing Handbook (CRC Press, Boca Raton, 2010)

    Google Scholar 

  53. L. Shih-Lien, Speeding up processing with approximation circuits. Computer 37(3), 67–73 (2004)

    Article  Google Scholar 

  54. J.Y.F. Tong, D. Nagle, R.A. Rutenbar, Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE Trans. Very Large Scale Integr. VLSI Syst. 8(3), 273–286 (2000)

    Article  Google Scholar 

  55. G.V. Varatkar, N.R. Shanbhag, Energy-efficient motion estimation using error-tolerance, in International Symposium on Low Power Electronics and Design (ISLPED’06), 4–6 October, pp. 113–118 (2006)

  56. K. Vasanth, S.N. Raj, S. Karthik, P.P. Mol, Fpga implementation of optimized sorting network algorithm for median filters, in International Conference on Emerging Trends in Robotics and Communication Technologies (INTERACT), 3–5 December, pp. 224–229 (2010)

  57. K. Vasanth, V.J.S. Kumar, A. Yogalakshmi, A. Sivasangari, A simple decision based neighborhood filter for the removal of salt and pepper noise. In International Conference on Emerging Trends in Computer Science and Information Technology (ICETCSIT), India, 30–31 March (2013)

  58. M.A. Vega-Rodríguez, J.M. Sánchez-Pérez, J.A. Gómez-Pulido, An FPGA-based implementation for median filter meeting the real-time requirements of automated visual inspection systems, in 10th Mediterranean Conference on Control and Automation (2002)

  59. A.K. Verma, P. Brisk, P. Ienne, Variable latency speculative addition: a new paradigm for arithmetic circuit design, in Design, Automation and Test in Europe (DATE ’08), 10–14 March, pp. 1250–1255 (2008)

  60. J. Von Neumann, Probabilistic logics and the synthesis of reliable organisms from unreliable components. Autom. Stud. 34, 43–98 (1956)

    Google Scholar 

  61. Z. Wang, A.C. Bovik, H.R. Sheikh, E.P. Simoncelli, Image quality assessment: from error visibility to structural similarity. IEEE Trans. Image Process. 13(4), 600–612 (2004)

    Article  Google Scholar 

  62. K.-C. Wu, D. Marculescu, Power-planning-aware soft error hardening via selective voltage assignment. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(1), 136–145 (2014)

    Article  Google Scholar 

  63. H. Yoshimoto, D. Arita, R. Taniguchi, Real-time communication for distributed vision processing based on imprecise computation model, in International Parallel and Distributed Processing Symposium, IEEE Computer Society, pp. 128–133 (2002)

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Correspondence to M. Monajati.

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Professor Seyed Mehdi Fakhraie passed away on December 7, 2014, aged 54.

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Monajati, M., Fakhraie, S.M. & Kabir, E. Approximate Arithmetic for Low-Power Image Median Filtering. Circuits Syst Signal Process 34, 3191–3219 (2015). https://doi.org/10.1007/s00034-015-9997-4

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