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Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA

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Abstract

Assessment of power consumption is very important for an efficient digital integrated circuit design. Dynamic power in digital programmable CMOS-based processors depends on the switching activity. Specifically in its subcomponents like FIR filter, power consumption can be directly related to the node switching activity. Minimization of power consumption can be done by reducing the transitions or dissimilarities in filter coefficients. Evolutionary algorithms (EAs) have been found to be very effective for optimized FIR filter design because of nonlinear, nondifferentiable, multimodal and nonconvex nature of the associated optimization problem. However, all the existing evolutionary optimization-based design techniques aim at meeting the frequency domain specifications without concentrating on minimizing power consumption. In the present work, a novel EA, i.e., hybrid artificial bee colony algorithm, has been proposed and further applied for FIR filter design. The filter design task aims at satisfying the dual objectives of meeting the desired frequency domain specifications and power minimization.

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Authors and Affiliations

  1. Department of Electrical Engineering, NIT, Raipur, 492010, India

    Atul Kumar Dwivedi, Subhojit Ghosh & Narendra D. Londhe

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  1. Atul Kumar Dwivedi
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  2. Subhojit Ghosh
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  3. Narendra D. Londhe
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Correspondence to Subhojit Ghosh.

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Dwivedi, A.K., Ghosh, S. & Londhe, N.D. Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA. Circuits Syst Signal Process 36, 156–180 (2017). https://doi.org/10.1007/s00034-016-0297-4

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