Abstract
In this paper, a new charge pump circuit for reducing charge and discharge currents with low power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump generates maximum 19.9 \(\upmu \)A current. This charge pump is designed and simulated in TSMC 0.18 \(\upmu \)m CMOS technology in order to be used in a delay-locked loop. One of the benefits of this circuit is its capability to be applied in a wide frequency range from 50 to 800 MHz with power consumption range of 410–740 \(\upmu \)W. The proposed charge pump exploits feedback loop in order to achieve suitable current matching and also has a good characteristics in high frequencies.
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C.C. Chung, C.L. Chang, A wide-range all-digital delay-locked loop in 65nm CMOS technology. In 2010 International Symposium on VLSI Design Automation and Test (VLSI-DAT), Apr 26. IEEE (2010), pp. 66–69
M. Estebsari, M. Gholami, M.J. Ghahramanpour, A wide frequency range delay line for fast-locking and low power delay-locked-loops. Analog Integrated Circuits and Signal Processing (2016), pp. 1–8
M. Gholami, A novel low power architecture for DLL-based frequency synthesizers. Circuits Syst. Signal Process. 32(2), 781–801 (2013)
M. Gholami, Total jitter of delay-locked loops due to four main jitter sources. IEEE Trans. Very Large Scale Integr. Syst. 24(6), 2040–2049 (2016)
M. Gholami, H. Rahimpour, G. Ardeshir, H. Miar-Naimi, A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers. Int. J. Cir. Theory Appl. 43(5), 566–578 (2015)
X. Hong, L. Zhiqun, W. Zhigong, L. Wei, Z. Li, A charge pump design for low-spur PLL. Chin. J. Semicond. Chin. Ed. 28(12), 1988 (2007)
M. Jalalifar, G.S. Byun, Near-threshold charge pump circuit using dual feedback loop. Electron. Lett. 49(23), 1436–1438 (2013)
C. Jia, A Delay-Locked Loop for Multiple Clock Phases/Delays Generation PhD report, Georgia Institute of Technology, December (2005)
N. Joram, R. Wolf, F. Ellinger, High swing PLL charge pump with current mismatch reduction. Electron. Lett. 50(9), 661–663 (2014)
J.S. Lee, M.S. Keel, S.I. Lim, S. Kim, Charge pump with perfect current matching characteristics in phase-locked loops. Electron. Lett. 36(23), 1907–1908 (2000)
P. Liu, P. Sun, J. Jung, D. Heo, PLL charge pump with adaptive body-bias compensation for minimum current variation. Electron. Lett. 48(1), 16–18 (2012)
W. Rhee, Design of high-performance CMOS charge pumps in phase-locked loops. In Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS’99. IEEE, Jul Vol. 2 (1999), pp. 545–548)
Y. Sun, L. Siek, P. Song, Design of a high performance charge pump circuit for low voltage phase-locked loops. In 2007 International Symposium on Integrated Circuits 2007 Sep 26. IEEE (2007), pp. 271–274
T. Yoshimura, S. Iwade, H. Makino, Y. Matsuda, Analysis of pull-in range limit by charge pump mismatch in a linear phase-locked loop. IEEE Trans. Circuits Syst. I Regul. Pap. 60(4), 896–907 (2013)
S. Zheng, Z. Li, A novel CMOS charge pump with high performance for phase-locked loops synthesizer. In 2011 IEEE 13th International Conference on Communication Technology (ICCT). IEEE (2011 Sep 25), pp. 1062–1065
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Estebsari, M., Gholami, M. & Ghahramanpour, M.J. A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops. Circuits Syst Signal Process 36, 3514–3526 (2017). https://doi.org/10.1007/s00034-016-0481-6
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DOI: https://doi.org/10.1007/s00034-016-0481-6