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A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS

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Abstract

A 15-bit, 85 MS/s hybrid flash-SAR ADC is presented. The proposed design combines modified tri-level switching technique with split capacitor technique to improve the power efficiency and sampling rate of the SAR block. The sampling switch was designed to achieve reduced settling time for DAC. Modified encoder block was used in flash ADC block and PMOS resistive ladder was used for better matching and linearity. To overcome high-frequency noise jitters in resistive ladder, parallel capacitors were added which act as low-pass filter. At 85 MS/s device consumes 650 uW and achieved an SNDR of 74.3 dB, ENOB of 12.06 with SFDR of 89 dBc. The proposed ADC is implemented in 1P-9M low K 90-nm CMOS process technology and occupies a chip area of 720 um \(\times \) 195 um.

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Authors and Affiliations

  1. Department of Electrical Engineering, COMSATS Institute of Information Technology, Wah Campus, Wah, Pakistan

    Anas Razzaq

  2. Department of Electrical Engineering, University of Engineering and Technology, Taxila, Pakistan

    Shabbir Majeed Chaudhry

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  1. Anas Razzaq
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  2. Shabbir Majeed Chaudhry
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Correspondence to Shabbir Majeed Chaudhry.

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Razzaq, A., Chaudhry, S.M. A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS. Circuits Syst Signal Process 37, 1452–1478 (2018). https://doi.org/10.1007/s00034-017-0629-z

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