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High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

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Abstract

We present a high-speed differential clocked voltage switch logic inverter operating at ultra-low supply voltages (ULV). Simulated data for the new gate are presented and compared to modified clocked voltage switch logic (CVSL). Preliminary measurements for ULV gates are presented. The increase in speed for supply voltages below 300 mV for the ULV gate presented is between 10 and 20 times compared to modified CVSL logic.

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References

  1. M. Alioto, Ultra-low power VLSI circuit design demystified and explained: a tutorial. IEEE Trans. Circuits Syst. I Regul. Pap. 59(1), 3–29 (2012)

    Article  MathSciNet  Google Scholar 

  2. Y. Berg, Novel ultra low-voltage and high speed domino CMOS logic, in International Conference on VLSI and System-on-chip (IEEE, Washington, 2010), pp. 225/228

  3. Y. Berg, O. Mirmotahari, Novel high-speed and ultra-low-voltage CMOS NAND and NOR domino gates, in CENICS 2012: The Fifth International Conference on Advances in Circuits, Electronics and Microelectronics (IARIA, 2012), pp. 5–10

  4. Y. Berg, O. Mirmotahari, Ultra low-voltage and high speed dynamic and static CMOS precharge logic, in 2012 Faible Tension Faible Consommation (FTFC) (IEEE, Washington, 2012), pp. 1–4

  5. K. Bernstein, High Speed CMOS Design Styles (Springer, Berlin, 1998)

    MATH  Google Scholar 

  6. J.B. Burr, A.M. Peterson, Ultra low power CMOS technology, in NASA VLSI Design Symposium (1991), pp. 4.2.1–4.2.13

  7. O. Mirmotahari, Y. Berg, Robustness of the ultra low-voltage domino gates CMOS, in Sixth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS 2013) (IARIA, 2013), pp. 7–12

  8. O. Mirmotahari, Y. Berg, Robust low-power CMOS precharge logic, in EEE Faible Tension Faible Consommation (FTFC) (IEEE, Washington, 2013), pp. 11–18

  9. N. Verma, J. Kwong, A. Chandrakasan, Nanometer MOSFET variation in minimum energy subthreshold circuits. IEEE Trans. Electron. Dev. 55(1), 847–854 (1995)

    Google Scholar 

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Authors and Affiliations

  1. Nanoelectronics, Department of Informatics, University of Oslo, Oslo, Norway

    Omid Mirmotahari & Yngvar Berg

Authors
  1. Omid Mirmotahari
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  2. Yngvar Berg
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Correspondence to Yngvar Berg.

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Mirmotahari, O., Berg, Y. High-Speed Digital Domino Logic for Ultra-Low Supply Voltages. Circuits Syst Signal Process 36, 4774–4788 (2017). https://doi.org/10.1007/s00034-017-0632-4

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  • DOI: https://doi.org/10.1007/s00034-017-0632-4

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