Abstract
Accurate modeling of CMOS logic gates for timing and power characterization is a very important task in integrated circuits technology since it facilitates significantly the design phase. Parametric models provide flexibility in determining the circuit performance in various design corners. However, the direct analysis of a complex CMOS gate aiming in an analytical and parametric model is a difficult and cumbersome task. An alternative way to model these gates is by using the equivalent inverter approach. According to this, an inverter with appropriate transistor widths is defined in order to present the same response with the complex gate it models. The challenge with this approach is to propose a simple method to predict the appropriate transistor widths of the equivalent inverter. Then, an analytical model for the CMOS inverter can be used to provide estimates for the complex gates. In this paper, a macro-modeling method is proposed for determining the transistor widths of the equivalent inverter and a technique for providing parametric expressions for these widths in terms of input transition time, output capacitive load, initial transistor width, supply voltage and temperature. A tool is developed to provide timing and power characterizations for the cells of a digital cell library, much faster than conventional numerical circuit simulators. The results prove the efficiency of the equivalent inverter approach in modeling complex gates.
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Notes
The internal energy consumption is defined as the energy flowing through the power or ground terminal (switching energy \(E_\mathrm{sw}\)) of the driving transistor block (nMOS or pMOS block) minus the dynamic energy (\(E_\mathrm{dyn}\)) which is the energy consumed on the output capacitive load.
Capacitance \(C_\mathrm{o}\) is used in gate characterization to model the total input capacitance of the gate(s) that follow.
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This work was supported by Hellenic Funds and by the European Regional Development Fund (ERDF) under the Hellenic National Strategic Reference Framework (ESPA) 2007–2013, according to Contract No. 11\(\varSigma \varUpsilon N\_5\_719\) project NANOTRIM.
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Messaris, I., Galani, C., Ntogramatzi, M. et al. An Evaluation of the Equivalent Inverter Modeling Approach. Circuits Syst Signal Process 37, 2665–2693 (2018). https://doi.org/10.1007/s00034-017-0692-5
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DOI: https://doi.org/10.1007/s00034-017-0692-5