Skip to main content
SpringerLink
Log in

Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

Data-access scheme affects the complexity of parallel architectures performing computation of multi-level two-dimensional (2-D) discrete wavelet transform (DWT). In this paper, we made a study on the data-access schemes considered in the existing parallel 2-D DWT architectures. Based on this study, a novel data-access scheme is proposed to avoid data multiplexing, which is common in the existing parallel architectures. Further, a block formulation is presented for vector computation of multi-level lifting 2-D DWT. A generic design of processing unit for computing one-level 2-D DWT is derived using the proposed block formulation. The proposed generic design resizes by a single parameter, i.e., the input-vector size. A regular and modular parallel architecture is derived using the generic processing unit design. The proposed parallel architecture easily scalable for higher block sizes as well as higher DWT levels without sacrificing its circuit regularity and modularity. This is an important feature of the proposed architecture. Comparison result shows that the proposed architecture for three-level DWT and block size 64 offers a saving in 24% area–delay–product (ADP) and 10% power consumption, and higher saving for higher block sizes than the best available similar structure without any overhead memory unlike the existing structure.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. C. Cheng, K.K. Parhi, High-speed VLSI implementation of 2-D discrete wavelet transform. IEEE Trans. Signal Process. 56(1), 393–403 (2008)

    Article  MathSciNet  MATH  Google Scholar 

  2. Y. Hu, C.C. Jong, A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT. IEEE Trans. Signal Process. 61(20), 4975–4987 (2013)

    Article  MathSciNet  MATH  Google Scholar 

  3. W. Jiang, A. Ortega, Lifting factorization-based discrete wavelet transform architecture design. IEEE Trans. Circuits Syst. Video Technol. 11(5), 651–657 (2001)

    Article  Google Scholar 

  4. Y.K. Lai, L.F. Lien, Y.C. Shih, A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform. IEEE Trans. Consum. Electron. 55(2), 400–407 (2009)

    Article  Google Scholar 

  5. H.Y. Liao, M.K. Mandal, B.F. Cockburn, Efficient architectures for 1-D and 2-D lifting-based wavelet transforms. IEEE Trans. Signal Process. 52(5), 1315–1326 (2004)

    Article  MathSciNet  MATH  Google Scholar 

  6. Y. Meyer, Wavelets: Algorithms and Applications (Society for Industrial and Applied Mathematics, Philadelphia, 1993)

    MATH  Google Scholar 

  7. P.K. Meher, B.K. Mohanty, J.C. Patra, Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform. IEEE Trans. Circuits Syst. II Express Briefs 55(2), 151–155 (2008)

    Article  Google Scholar 

  8. B.K. Mohanty, P.K. Meher, Memory efficient modular VLSI architecture for high throughput and low-latency implementation of multilevel lifting 2-D DWT. IEEE Trans. Signal Process. 59(5), 2072–2084 (2011)

    Article  MathSciNet  MATH  Google Scholar 

  9. B.K. Mohanty, P.K. Meher, Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT. IEEE Trans. Circuits Syst. Video Technol. 23(2), 353–363 (2012)

    Article  Google Scholar 

  10. B.K. Mohanty, A. Mahajan, P.K. Meher, Area and power-efficient architecture for high-throughput implementation of lifting 2-D DWT. IEEE Trans. Circuits Syst. II Express Briefs 59(7), 434–438 (2012)

    Article  Google Scholar 

  11. B.K. Mohanty, P.K. Meher, T. Srikanthan, Critical-path optimization for efficient hardware realization of lifting and flipping DWTs, in IEEE International Symposium on Circuits and Systems (ISCAS, Portugal, 2015), pp. 1186–1189

  12. B.K. Mohanty, A. Choubey, Efficient design for Radix-8 booth multiplier and its application in lifting 2-D DWT. Circuits Syst. Signal Process. (CSSP) 36, 1129–1149 (2017)

    Article  Google Scholar 

  13. A. Skodars, C. Christopoulos, T.E. brahimi, The JPEG 2000 still image compression standard. IEEE Signal Process. Mag. 18(5), 36–58 (2001)

    Article  Google Scholar 

  14. W. Sweldens, The lifting scheme: a custom-designed construction of bi-orthogonal wavelets. Appl. Comput. Harmon. Anal. 3(2), 186–200 (1996)

    Article  MathSciNet  MATH  Google Scholar 

  15. X. Tian, L. Wu, Y.-H. Tan, J.-W. Tian, Efficient multi-input/multi-output VLSI architecture for two-dimensional lifting-based discrete wavelet transform. IEEE Trans. Comput. 60(8), 1207–1211 (2011)

    Article  MathSciNet  MATH  Google Scholar 

  16. M. Vishwanath, The recursive pyramid algorithm for the discrete wavelet transform. IEEE Trans. Signal Process. 42(3), 673–676 (1994)

    Article  Google Scholar 

  17. P.C. Wu, L.G. Chen, An efficient architecture for two-dimensional discrete wavelet transform. IEEE Trans. Circuits Syst. Video Technol. 11(4), 536–545 (2001)

    Article  Google Scholar 

  18. C.Y. Xiong, J. Tian, J. Liu, Efficient architectures for two-dimensional discrete wavelet transform using lifting scheme. IEEE Trans. Image Process. 16(3), 607–614 (2007)

    Article  MathSciNet  Google Scholar 

  19. C. Zhang, C. Wang, M.O. Ahmad, A pipeline VLSI architecture for fast computation of the 2-D discrete wavelet transform. IEEE Trans. Circuits Syst. I Regul. Pap. 59(8), 1775–1785 (2012)

    Article  MathSciNet  Google Scholar 

  20. W. Zhang, Z. Jiang, Z. Gao, Y. Liu, An efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Trans. Circuits Syst. II Express Briefs 59(3), 158–162 (2012)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jaypee University of Engineering and Technology, AB-Road, Raghogarh, Guna, Madhya Pradesh, 473226, India

    Abhishek Choubey & Basant Kumar Mohanty

Authors
  1. Abhishek Choubey
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Basant Kumar Mohanty
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Abhishek Choubey.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Choubey, A., Mohanty, B.K. Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT. Circuits Syst Signal Process 37, 4482–4503 (2018). https://doi.org/10.1007/s00034-018-0775-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-018-0775-y

Keywords

Search

Navigation