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A Low-Cost Tiny-Size Successive Approximation ADC for Applications Requiring Low-Resolution Conversion with Moderate Sampling Rate

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Abstract

The required silicon die area of successive approximation analog-to-digital converters (SA-ADCs) increases rapidly with ADC resolution. In particular, a main design challenge for SA-ADCs is the number of unit capacitors required for the internal charge distribution capacitive-array digital-to-analog converter (DAC), which increases exponentially with a monotonic increase in the number of the output bits. Therefore, the overall performance of the final design is affected by the huge die area and, in turn, the switching energy of the capacitive-array DAC. In this article, a tiny-size MOSFET-only SA-ADC topology is proposed for those applications which require a low-resolution and moderate to high sampling-rate analog-to-digital converters prior to digital processing units. To this end, the widely used metal–insulator–metal (MIM) capacitors of mixed-signal CMOS technologies are replaced with area-efficient MOS capacitors available in every technology. The effectiveness of this implementation is validated through successful simulation of a 5-bit 20 MS/s MOSFET-only SA-ADC in a low-cost 0.18-µm digital CMOS technology. The ADC consumes a total power of 76.88 µW from a 1.2-V voltage supply, while it occupies a die size of only 190 µm2. This area is roughly 40% lower than 310 µm2, the die area of an equivalent design based on MIM capacitors.

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Authors and Affiliations

  1. Department of Electrical Engineering, Payame Noor University, 19395-3697, Tehran, Iran

    Hamed Aminzadeh

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  1. Hamed Aminzadeh
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Correspondence to Hamed Aminzadeh.

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Aminzadeh, H. A Low-Cost Tiny-Size Successive Approximation ADC for Applications Requiring Low-Resolution Conversion with Moderate Sampling Rate. Circuits Syst Signal Process 38, 242–258 (2019). https://doi.org/10.1007/s00034-018-0854-0

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  • DOI: https://doi.org/10.1007/s00034-018-0854-0

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