Abstract
Systolic designs are considered as suitable candidate for high-speed VLSI realization for their inherent advantages of simplicity, regularity, modularity, and local interconnections. During the past few decades several systolic designs of finite field multipliers have been proposed in the literature. They are popularly used to achieve very high-throughput rate without any centralized control. But, all these designs incorporate heavy systolic penalties in terms of register complexity and latency of computation. We have analyzed here the hidden systolic penalties in those multipliers and proposed a digit-level systolic-like structure and a super-systolic-like structure for finite field multiplication. We have shown that the key issues to obtain such designs are the choice of design layout and digit size which substantially affect the register complexity, critical path, and latency. We have determined the optimal digit size and design layout to reduce the systolic penalties and at the same time to achieve lower critical path, higher-throughput rate, and lower latency with less register complexity with lower overall area complexity.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
T. Beth, D. Gollmann, Algorithm engineering for public key algorithms. IEEE J. Sel. Areas Commun. 7(4), 458–465 (1989)
J.H. Guo, C.L. Wang, Digit-serial systolic multiplier for finite fields \(GF(2^m)\). IEE Proc. Comput. Digital Tech. 145(2), 143–148 (1998)
D. Hankerson, A. Menezes, S. Vanstone, Guide to Elliptic Curve Cryptography (Springer, Berlin, Heidelberg, 2003)
A. Hariri, A.R. Masoleh, Digit-level semi-systolic and systolic structures for the shifted polynomial basis multiplication over binary extension fields. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 19(11), 2125–2129 (2011)
F.R. Henriguez, C.K. Koc, Parallel multipliers based on special irreducible pentanomials. IEEE Trans. Comput. 52(12), 1535–1542 (2003)
I.S. Hsu, T.K. Truong, L.J. Deutsch, I.S. Reed, A comparison of VLSI architecture of finite field multipliers using dual, normal, or Standard bases. IEEE Trans. Comput. 37(6), 735–739 (1988)
J.L. Imana, J.M. Sanchez, F. Tirado, Bit-parallel finite field multipliers for irreducible trinomials. IEEE Trans. Computers. 55(5), 520–533 (2006)
S.K. Jain, L. Song, K.K. Parhi, Efficient semisystolic architectures for finite-field arithmetic. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 6(1), 101–113 (1998)
C.H. Kim, C.P. Hong, S. Kwon, A digit-serial multiplier for finite field \(GF(2^m)\). IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 13(4), 476–483 (2005)
C.Y. Lee, Low complexity bit-parallel systolic multiplier over \(GF(2^m)\) using irreducible trinomials. IEE Proc. Comput. Digit. Tech. 150(1), 39–42 (2003)
C.Y. Lee, J.S. Horng, I.C. Jou, E.H. Lu, Low complexity bit parallel systolic Montgomery multipliers for special class of \(GF(2^m)\). IEEE Trans. Comput. 54(9), 1061–1070 (2005)
R. Lidl, H. Niederreiter, Introduction to Finite Fields and their Applications (Cambridge University Press, Cambridge, 1986)
J. Lopez, R. Dahab, An Overview of Elliptic Curve Cryptography. Technical Report IC-00-10, State University of Campinas, Brazil (2000)
A.R. Masoleh, M.A. Hasan, Low complexity bit parallel architectures for polynomial basis multiplication over \(GF(2^m)\). IEEE Trans. Comput. 53(8), 945–959 (2004)
P.K. Meher, Systolic and super-systolic multipliers for finite field \({GF(2^m)}\) based on irreducible trinomials. IEEE Trans. Circuits Syst. I Regul. Pap. 55(4), 1031–1040 (2008)
B.K. Meher, P.K. Meher, An efficient look-up table-based approach for multiplication over \(GF(2^m)\) generated by trinomials. Circuits Signals Signal Process. 32, 2623–2638 (2013)
National Institute of Standards and Technology (NIST). http://www.csrc.nist.gov/publications
P.A. Scott, S.E. Tavares, L.E. Peppard, A Fast VLSI multiplier for \(GF(2^m)\). IEEE J. Sel. Areas Commun. 4(1), 62–66 (1986)
L. Song, K.K. Parhi, Low-energy digit-serial/parallel finite field multipliers. J. VLSI SDignal Process. Syst. Signal Image Video Technol. 19, 149–166 (1998)
W. Tang, H. Wu, M. Ahmadi, VLSI implementation of bit-parallel word-serial multiplier in \(GF(2^{233})\), in Third International IEEE-NEWCAS Conference, 399–402 (2005)
C.L. Wang, J.L. Lin, Systolic array implementation of multipliers for finite fields \(GF(2^m)\). IEEE Trans. Circuits Syst. 38(7), 796–800 (1991)
H. Wu, Low complexity bit-parallel multiplier for a class of finite fields, in Proceedings of International Conference on Communications, Circuits and Systems, vol. 4, pp. 565–568 (2006)
J. Xie, P.K. Meher, Z. Mao, High-throughput digit-level systolic multiplier over \(GF(2^m)\) based on irreducible trinomials. IEEE Trans. Circuits Syst. II Exp. Briefs 62(5), 481–485 (2015)
C.S. Yeh, I.S. Reed, T.K. Truong, Systolic multipliers for finite fields \(GF(2^m)\). IEEE Trans. Comput. C–33(4), 357–360 (1984)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Meher, B.K., Meher, P.K. Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields. Circuits Syst Signal Process 38, 774–790 (2019). https://doi.org/10.1007/s00034-018-0884-7
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-018-0884-7