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Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier

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Abstract

This work presents and validates the design of a four-quadrant analog multiplier based on the bulk-driven technique. Using the source–gate as well as the bulk–source voltages of a PMOS transistor as input ports, the multiplication task can be achieved. The AC signals are injected into the bulk terminals by means of a very-low-frequency programmable high-pass RC network which also serves to set its proper DC operation point. Although two RC networks are required, this multiplication cell is composed of only seven PMOS transistors and two coupling capacitors which makes it a very compact circuit. Furthermore, no preprocessed signals like the sum of \(\pm \,v_x \pm \,v_y\) are required at the input ports. The implemented circuit shows a bandwidth of 50 MHz for an output capacitance of 40 pF and a THD lower than 1\(\%\) for gate/bulk input amplitudes below 0.2 Vp. The power consumption of the multiplication core is 660 \(\upmu \)W and 2.6 mW including output buffers. In order to simulate and fabricate this circuit, an ON Semi 0.50 \(\upmu \)m CMOS standard technology is used, showing a silicon area consumption of \(280\,\upmu \hbox {m} \times 400\,\upmu \)m including output buffers. The proposed multiplier is suitable for biomedical, AM modulation, base-band modulation and analog computation.

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Acknowledgements

The authors would like to thank to National Council of Science and Technology (CONACyT), Mexico, for the scholarships \(\#\)371630 and \(\#\)477685.

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Authors and Affiliations

  1. Facultad de Ciencias de la Electronica, Benemerita Universidad Autonoma de Puebla (BUAP), Puebla, Mexico

    Gregorio Zamora-Mejia, Alejandra Diaz-Armendariz, Hector Santiago-Ramirez & Jose Miguel Rocha-Perez

  2. Universidad Iberoamericana (IBERO), Puebla, Mexico

    Gregorio Zamora-Mejia

  3. Instituto Tecnologico de Puebla, Puebla, Mexico

    Carlos Arturo Gracios-Marin

  4. Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico

    Jose Miguel Rocha-Perez & Alejandro Diaz-Sanchez

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  1. Gregorio Zamora-Mejia
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  2. Alejandra Diaz-Armendariz
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  3. Hector Santiago-Ramirez
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  4. Jose Miguel Rocha-Perez
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  5. Carlos Arturo Gracios-Marin
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  6. Alejandro Diaz-Sanchez
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Correspondence to Gregorio Zamora-Mejia.

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Zamora-Mejia, G., Diaz-Armendariz, A., Santiago-Ramirez, H. et al. Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier. Circuits Syst Signal Process 38, 1547–1560 (2019). https://doi.org/10.1007/s00034-018-0945-y

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  • DOI: https://doi.org/10.1007/s00034-018-0945-y

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