Skip to main content
SpringerLink
Log in

Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n − 1 Adder and Multiplier

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

By increasing the length of input operands, standard binary number representation cannot satisfy the need for area-time-power efficient systems due to carry propagation chain problem. Redundant residue number system (RRNS) would be an appropriate solution to this demand as it divides large numbers to smaller ones on which the arithmetic operations could be performed in parallel. Maximally redundant signed-digit RNS (MRSD-RNS) has been recently presented as a low-power RRNS because the addition unit based on this number system consumes the least power among the existing RRNS encodings. In this work, a low-power MRSD-RNS multiplier for modulo 2n− 1 is proposed for the first time. The implementation results based on the TSMC-90 nm CMOS Technology indicate that our proposed design outperforms power, area, power-delay-product and area-delay-product in comparison with the efficient existing RRNS multipliers for the cases in which delay is not a limiting factor. It has also the least delay among the existing high-radix RRNS multipliers. Therefore, the proposed multiplier can meet the strict area-time-energy constraints which can be used as the core of signal processor in many applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22

Similar content being viewed by others

References

  1. A. Armand, S. Timarchi, Low power design of binary signed digit residue number system adder, in 24th Iranian Conference on Electrical Engineering (ICEE) (2016), pp. 844–848

  2. A. Avizienis, Signed-digit number representations for fast parallel arithmetic. IRE Trans. Electron. Comput. 10, 389–400 (1961)

    Article  MathSciNet  Google Scholar 

  3. H. Garner, The residue number system. IRE Trans. Electron. Comput. EC-8, 140–147 (1959)

    Article  Google Scholar 

  4. G. Jaberipur, B. Parhami, M. Ghodsi, Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems I. IEEE Trans. Circuits Syst. 52, 28 (2005)

    Article  MathSciNet  MATH  Google Scholar 

  5. M. Khan, S. Din, S. Jabbar, M. Gohar, H. Ghayvat, S.C. Mukhopadhyay, Context-aware low power intelligent SmartHome based on the Internet of things. Comput. Electr. Eng. 52, 208–222 (2016)

    Article  Google Scholar 

  6. I. Koren, Computer Arithmetic Algorithms (Universities Press, New York, 2002)

    MATH  Google Scholar 

  7. X. Liu, E.S. Sinencio, An 86% efficiency 12 µW self-sustaining PV energy harvesting system with hysteresis regulation and time-domain MPPT for IOT smart nodes. IEEE J. Solid-State Circuits 50(6), 1424–1437 (2015)

    Article  Google Scholar 

  8. A.S. Madhukumar, F. Chin, Enhanced architecture for residue number system-based CDMA for high-rate data transmission. IEEE Trans. Wirel. Commun. 3, 1363–1368 (2004)

    Article  Google Scholar 

  9. H. Marzouqi, M. Al-Qutayri, K. Salah, Review of Elliptic Curve Cryptography processor designs. Microprocess. Microsyst. 39(2), 97–112 (2015)

    Article  Google Scholar 

  10. M.C. Mekhallalati, M.K. Ibrahim, New high radix maximally-redundant signed digit adder, in IEEE International Symposium on Circuits and Systems, vol. 1 (1999), pp. 459–462

  11. K. Navi, A.S. Molahosseini, M. Esmaeildoust, How to teach residue number system to computer scientists and engineers. IEEE Trans. Educ. 54, 156–163 (2011)

    Article  Google Scholar 

  12. B. Parhami, Generalized signed-digit number systems: a unifying framework for redundant number representations. IEEE Trans. Comput. 39(1), 89–98 (1990)

    Article  Google Scholar 

  13. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs (Oxford University Press, Inc., Oxford, 2009)

    Google Scholar 

  14. D.S. Phatak, I. Koren, Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains. IEEE Trans. Comput. 43, 880–891 (1994)

    Article  MATH  Google Scholar 

  15. D.S. Phatak, T. Goff, I. Koren, Constant-time addition and simultaneous format conversion based on redundant binary representations. IEEE Trans. Comput. 50, 1267–1278 (2001)

    Article  Google Scholar 

  16. A. Safari, C.V. Niras, Y. Kong, Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling. VLSI J. Integr. 53, 145–156 (2016)

    Article  Google Scholar 

  17. M. Salim, A.O. Akkirman, M. Hidayetoglu, L. Gurel, Comparative benchmarking: matrix multiplication on a multicore coprocessor and a GPU, in Computational Electromagnetics International Workshop (CEM) (IEEE, 2015)

  18. M. Saremi, S. Timarchi, Efficient modular binary signed-digit multiplier for the moduli set {2n − 1, 2n, 2n + 1}. CSI J. Comput. Sci. Eng. 9(2 & 4(b)), 52–62 (2011)

    Google Scholar 

  19. M. Saremi, S. Timarchi, Efficient 1-out-of-3 binary signed-digit multiplier for the moduli set {2n − 1, 2n, 2n + 1}, in 2013 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS) (IEEE, 2013)

  20. S. Timarchi, K. Navi, Efficient class of redundant residue number system, in Proc. IEEE Int. Symp. WISP (2007), pp. 475–480

  21. S. Timarchi, K. Navi, Arithmetic circuits of redundant SUT-RNS. IEEE Trans. Instrum. Meas. 58(9), 2959–2968 (2009)

    Article  Google Scholar 

  22. S. Timarchi, M. Fazlali, Generalised fault-tolerant stored-unibit transfer residue number system multiplier for moduli set {2n − 1, 2n, 2n + 1}. IET Comput. Digit. Tech. 6(5), 269–276 (2012)

    Article  Google Scholar 

  23. S. Timarchi, P. Ghayour, A. Shahbahrami, A novel high-speed low-power binary signed-digit adder, in 16th CSI International symposium on Computer Architecture and Digital Systems (CADS) (2012), pp. 357–363

  24. S. Timarchi, M. Saremi, M. Fazlali, G. Georgi, High-speed binary signed-digit RNS adder with posibit and negabit encoding, in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) (IEEE, 2013), pp. 58–59

  25. S. Timarchi, N. Akbarzadeh, A. Hamidi, Maximally redundant high-radix signed-digit residue number system, in 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) (2015)

  26. E. Vassalos, D. Bakalis, Combined SD-RNS constant multiplication, in 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (2009), pp. 172–179

  27. V. Volkov, J.W. Demmel, Benchmarking GPUs to tune dense linear algebra, in International Conference for High Performance Computing, Networking, Storage and Analysis, 2008. SC 2008 (IEEE, 2008)

  28. Z. Wang, Y. Liu, Y. Sun, Y. Li, D. Zhang, H. Yang, An energy-efficient heterogeneous dual-core processor for Internet of Things, in IEEE International Symposium on Circuits and Systems (ISCAS) (2015), pp. 2301–2304

  29. Sh. Wei, K. Shimizu, Residue arithmetic circuits using a signed-digit number representation, in IEEE International Symposium on Circuits and Systems

  30. Sh. Wei, J. Changjun, Residue signed-digit arithmetic and the conversions between residue and binary numbers for a Four-Moduli Set, in 2012 11th International Symposium on Distributed Computing and Applications to Business, Engineering & Science (DCABES) (IEEE, 2012)

  31. M. Zhang, Sh. Wei, High-speed modular multipliers based on a new binary signed-digit adder tree structure, in Ninth International Symposium on Distributed Computing and Applications to Business, Engineering and Science (2010), pp. 615–619

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Shahid Beheshti University, G.C., Tehran, Iran

    Somayeh Timarchi & Negar Akbarzadeh

Authors
  1. Somayeh Timarchi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Negar Akbarzadeh
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Somayeh Timarchi.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Timarchi, S., Akbarzadeh, N. Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n − 1 Adder and Multiplier. Circuits Syst Signal Process 38, 2138–2164 (2019). https://doi.org/10.1007/s00034-018-0957-7

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-018-0957-7

Keywords

Search

Navigation