Abstract
Electrocardiogram monitoring is crucial for the prevention and treatment of cardiovascular diseases. To record the electrical activity of different regions of the heart and manage the signals generated for long-term monitoring, a compression algorithm is necessary. This letter presents a novel compressor and decompressor able to support 3-lead compression without increasing hardware costs and area. The experimental results demonstrated that the bit compression ratio and power consumption can be improved by the proposed architecture. The effectiveness of this approach was verified by fabricating a chip using 0.18-\(\upmu \hbox {m}\) complementary metal-oxide-semiconductor technology. The proposed encoder has an operating frequency of 20 MHz and a gate count of 4.8K, and the proposed decoder has an operating frequency of 10 MHz and a gate count of 4.8K.
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Acknowledgements
The authors would like to acknowledge chip fabrication support provided by Taiwan Semiconductor Research Institute (TSRI), Taiwan, R. O. C. The authors would like to thank the Particle Physics and Beam Delivery Core Laboratory of Institute for Radiological Research, Chang Gung University/Chang Gung Memorial Hospital, Linkou, for their assistance.
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This work was supported in part by the Ministry of Science and Technology of Taiwan under project MOST 107-2221-E-182-066 and the Chang Gung Memorial Hospital, Linkou under project CMRPD2H0301, CMRPD2G0312, CMRPD2H0051, and CIRPD2F0013.
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Chen, YH., Tseng, YH., Chu, PH. et al. VLSI Implementation of a Cost-Efficient 3-Lead Lossless ECG Compressor and Decompressor. Circuits Syst Signal Process 39, 1665–1671 (2020). https://doi.org/10.1007/s00034-019-01198-8
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DOI: https://doi.org/10.1007/s00034-019-01198-8