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Performance Analysis of Solid-State Fractional Capacitor-Based Analog \(\hbox {PI}^\lambda \hbox {D}^{\mu }\) Controller

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Abstract

This work reports analog implementation of \(\hbox {PI}^\lambda \hbox {D}^\mu \) controller realized by solid-state fractional capacitor. The fractional integrator is implemented with a solid-state fractional capacitor fabricated by the authors, and the fractional differentiator circuit is implemented using optimal pole–zero interlacing algorithm. The paper proposes a tuning algorithm for finding the parameters of the fractional \(\hbox {PI}^{\lambda }\hbox {D}^{\mu }\) controller to get the desired time domain performance. Using the tuning algorithm, the combinations of \(\lambda \), \(\mu \) and gain values of the controller are evaluated on a DC motor emulator to limit % overshoot \(\le \) 12% and settling time < 13 ms. The performance of the controller (with \(\lambda = \mu = 0.4\)) on speed regulation of DC motor emulator has also been discussed in detail both in simulation and in hardware.

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Notes

  1. in which numerical optimization is carried out to meet the step response design requirements

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Acknowledgements

The authors would like to thank Swapnil Khulbalkar and Saket Sehgal for their valuable suggestions.

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Authors and Affiliations

  1. Department of EE, Indian Institute of Technology Kharagpur, Kharagpur, West Begal, India

    Dina A. John & Karabi Biswas

  2. Department of EE, VNIT, Nagpur, Maharashtra, 440010, India

    M. V. Aware & A. S. Junghare

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  1. Dina A. John
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Correspondence to Karabi Biswas.

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This article is based upon work of European “COST Action CA15225” which is on “Fractional-order systems; analysis, synthesis and their importance for future design”.

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John, D.A., Aware, M.V., Junghare, A.S. et al. Performance Analysis of Solid-State Fractional Capacitor-Based Analog \(\hbox {PI}^\lambda \hbox {D}^{\mu }\) Controller. Circuits Syst Signal Process 39, 1815–1830 (2020). https://doi.org/10.1007/s00034-019-01255-2

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