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Configurable Rotation Matrix of Hyperbolic CORDIC for Any Logarithm and Its Inverse computation

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Abstract

In this paper, we propose a configurable rotation matrix for Hyperbolic COordinate Rotation DIgital Computer (CORDIC) to compute any logarithm and inverse logarithm. The rotation matrix of the conventional Hyperbolic CORDIC computes only natural logarithm and natural inverse logarithm whereas the proposed rotation matrix configures the Hyperbolic CORDIC to compute any logarithm and inverse logarithm. Subsequently, an architecture for configurable Hyperbolic CORDIC has been designed based on the proposed rotation matrix. An extensive vector matching is performed to validate the proposed architecture. Finally, an ASIC implementation for configurable Hyperbolic CORDIC has been performed using TSMC 45-nm CMOS technology @ 1 GHz frequency. The accuracy of the proposed configurable Hyperbolic CORDIC is same as conventional Hyperbolic CORDIC. The proposed approach saves 19.22% on chip area and 17.52% power consumption for decimal logarithm computation and 18.55% on chip area and 16.12% power consumption for inverse logarithm computation when compared with the state of the art approaches.

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References

  1. A. Acharyya, K. Maharatna, B.M. Al-Hashimi, J. Reeve, Coordinate rotation based low complexity N-D FastICA algorithm and architecture. IEEE Trans. Signal Process. 59(8), 3997–4011 (2011). https://doi.org/10.1109/TSP.2011.2150219

    Article  MathSciNet  MATH  Google Scholar 

  2. S. Aggarwal, P.K. Meher, K. Khare, Scale-free hyperbolic CORDIC processor and its application to waveform generation. IEEE Trans. Circuits Syst. I Regul. Pap. 60(2), 314–326 (2013). https://doi.org/10.1109/TCSI.2012.2215778

    Article  MathSciNet  Google Scholar 

  3. S. Aggarwal, P.K. Meher, K. Khare, Concept, design, and implementation of reconfigurable CORDIC. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(4), 1588–1592 (2016). https://doi.org/10.1109/TVLSI.2015.2445855

    Article  Google Scholar 

  4. L. Bangqiang, H. Ling, Y. Xiao, Base-N logarithm implementation on FPGA for the data with random decimal point positions. In IEEE 9th International Colloquium on Signal Processing and its Applications, Kuala Lumpur (2013), pp. 17–20. https://doi.org/10.1109/CSPA.2013.6530006

  5. S. Bass, R. Harber, X. Hu, Expanding the range of convergence of the CORDIC algorithm. IEEE Trans. Comput. 40, 13–21 (1991). https://doi.org/10.1109/12.67316

    Article  Google Scholar 

  6. R.C. Chang, C. Lin, K. Lin, C. Huang, F. Chen, Iterative \(QR\) decomposition architecture using the modified Gram–Schmidt algorithm for MIMO systems. IEEE Trans. Circuits Syst. I Regul. Pap. 57(5), 1095–1102 (2010). https://doi.org/10.1109/TCSI.2010.2047744

    Article  MathSciNet  Google Scholar 

  7. D. De Caro, N. Petra, A.G.M. Strollo, Efficient logarithmic converters for digital signal processing applications. IEEE Trans. Circuits Syst. II Express Briefs 58(10), 667–671 (2011). https://doi.org/10.1109/TCSII.2011.2164159

    Article  Google Scholar 

  8. C. Dick, F.J. Harris, Configurable logic for digital communications: some signal processing perspectives. IEEE Commun. Mag. 37(8), 107–111 (1999). https://doi.org/10.1109/35.783133

    Article  Google Scholar 

  9. R. Gutierrez, J. Valls, Low cost hardware implementation of logarithm approximation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(12), 2326–2330 (2011). https://doi.org/10.1109/TVLSI.2010.2081387

    Article  Google Scholar 

  10. E.L. Hall, D.D. Lynch, S.J. Dwyer, Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Trans. Comput. C–19(2), 97–105 (1970). https://doi.org/10.1109/T-C.1970.222874

    Article  MATH  Google Scholar 

  11. G. Helvacioglu, A.B.K.Y.K. Alp, C. Kasnakoglu, Reduced CORDIC based logarithmic convertor. In 25th Signal Processing and Communications Applications Conference (SIU). Antalya (2017), pp. 1–4. https://doi.org/10.1109/SIU.2017.7960483

  12. Y.H. Hu, CORDIC-based VLSI architectures for digital signal processing. IEEE Signal Process. Mag. 9(3), 16–35 (1992). https://doi.org/10.1109/79.143467

    Article  Google Scholar 

  13. Y.H. Hu, Z. Wu, An efficient CORDIC array structure for the implementation of discrete cosine transform. IEEE Trans. Signal Process. 43(1), 331–336 (1995). https://doi.org/10.1109/78.365320

    Article  Google Scholar 

  14. T. Juang, S. Chen, H. Cheng, A lower error and ROM-free logarithmic converter for digital signal processing applications. IEEE Trans. Circuits Syst. II Express Briefs 56(12), 931–935 (2009). https://doi.org/10.1109/TCSII.2009.2035270

    Article  Google Scholar 

  15. J. Kaur, L. Sood, Comparison between various types of adder topologies. In IJCST, vol. 6, no. 1 (2015)

  16. Z. Liu, K. Dickson, J.V. McCanny, Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. IEEE Trans. Circuits Syst. I Regul. Pap. 52(4), 755–765 (2005)

    Article  Google Scholar 

  17. Y. Liu, L. Fan, T. Ma, A modified CORDIC FPGA implementation for wave generation. Circuits Syst. Signal Process. 33(1), 321–329 (2014). https://doi.org/10.1007/s00034-013-9638-8

    Article  Google Scholar 

  18. M. Lohning, T. Hentschel, G. Fettweis, Digital down conversion in software radio terminals. In 10th European Signal Processing Conference, Tampere (2000), pp. 1–4

  19. Y. Luo, Y. Wang, H. Sun, Y. Zha, Z. Wang, H. Pan, CORDIC-based architecture for computing Nth root and its implementation. IEEE Trans. Circuits Syst. I Regul. Pap. (2018). https://doi.org/10.1109/TCSI.2018.2835822

    Article  Google Scholar 

  20. L. Ma, K. Dickson, J. McAllister, J. McCanny, QR decomposition-based matrix inversion for high performance embedded MIMO receivers. IEEE Trans. Signal Process. 59(4), 1858–1867 (2011). https://doi.org/10.1109/TSP.2011.2105485

    Article  Google Scholar 

  21. P. Meher, J. Valls, T.-B. Juang, K. Sridharan, K. Maharatna, 50 years of CORDIC: algorithms, architectures, and applications. IEEE Trans. Circuits Syst. I Regul. Pap. 56(9), 1893–1907 (2009)

    Article  MathSciNet  Google Scholar 

  22. S. Mopuri, A. Acharyya, Low-complexity methodology for complex square-root computation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(11), 3255–3259 (2017). https://doi.org/10.1109/TVLSI.2017.2740343

    Article  Google Scholar 

  23. S. Mopuri, S. Bhardwaj, A. Acharyya, Coordinate rotation based design methodology for square root and division computation. IEEE Trans. Circuits. Syst. II Express Briefs (2018). https://doi.org/10.1109/TCSII.2018.2878599

    Article  Google Scholar 

  24. S.D. Munoz, J. Hormigo, High-throughput FPGA implementation of QR decomposition. IEEE Trans. Circuits Syst. II Express Briefs 62(9), 861–865 (2015). https://doi.org/10.1109/TCSII.2015.2435753

    Article  Google Scholar 

  25. Mencer Oskar, Luc Semeria, Martin Morf, Jean-Marc Delosme, Application of reconfigurable CORDIC architectures. J. VLSI Signal Process. Syst. Signal Image Video Technol. 24(2–3), 211–221 (2000)

    Google Scholar 

  26. S.Y. Park, Y.J. Yu, Fixed-point analysis and parameter selections of MSR-CORDIC with applications to FFT designs. IEEE Trans. Signal Process. 60(12), 6245–6256 (2012). https://doi.org/10.1109/TSP.2012.2214218

    Article  MathSciNet  MATH  Google Scholar 

  27. S. Paul, N. Jayakumar, S.P. Khatri, A fast hardware approach for approximate, efficient logarithm and antilogarithm computations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(2), 269–277 (2009). https://doi.org/10.1109/TVLSI.2008.2003481

    Article  Google Scholar 

  28. J. Qiu, K. Sun, T. Wang, H. Gao, Observer-based fuzzy adaptive event-triggered control for pure-feedback nonlinear systems with prescribed performance. IEEE Trans. Fuzzy Syst. (2019). https://doi.org/10.1109/TFUZZ.2019.2895560

    Article  Google Scholar 

  29. M.J. Schulte, J.E. Stine, Approximating elementary functions with symmetric bipartite tables. IEEE Trans. Comput. 48(8), 842–847 (1999). https://doi.org/10.1109/12.795125

    Article  Google Scholar 

  30. K. Sun, S. Mou, J. Qiu, T. Wang, H. Gao, Adaptive fuzzy control for nontriangular structural stochastic switched nonlinear systems with full state constraints. IEEE Trans. Fuzzy Syst. 27(8), 1587–1601 (2019). https://doi.org/10.1109/TFUZZ.2018.2883374

    Article  Google Scholar 

  31. A. Tang, Y. Li, F. Han, Z. Zhang, CORDIC-based FFT real-time processing design and FPGA implementation. In IEEE 12th International Colloquium on Signal Processing & Its Applications (CSPA). Malacca City, pp. 233–236 (2016). https://doi.org/10.1109/CSPA.2016.7515837

  32. J. Valls, T. Sansaloni, A. Perez-Pascual, V. Torres, V. Almenar, The use of CORDIC in software defined radios: a tutorial. IEEE Commun. Mag. 44(9), 46–50 (2006). https://doi.org/10.1109/MCOM.2006.1705978

    Article  Google Scholar 

  33. Á. Vazquez, J. Villalba, E. Antelo, Computation of decimal transcendental functions using the CORDIC algorithm. In 19th IEEE Symposium on Computer Arithmetic. Portland, OR (2009), pp. 179–186. https://doi.org/10.1109/ARITH.2009.29

  34. J.E. Volder, The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput. EC–8(3), 330–334 (1959). https://doi.org/10.1109/TEC.1959.5222693

    Article  Google Scholar 

  35. J.E. Volder, The birth of CORDIC. J. VLSI Signal Process. 25, 101–105 (2000). https://doi.org/10.1023/A:1008110704586

    Article  Google Scholar 

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Correspondence to Amit Acharyya.

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This work is partially funded by the Science and Engineering Research Board(SERB), Government of India for the project entitled “Intelligent IoT enabled Autonomous Structural Health Monitoring System for Ships, Aeroplanes, Trains and Automobiles” under the Impacting Research Innovation and Technology (IMPRINT) program with the Grant Number IMP/2018/000375. All the Computer-Aided Design tools are supported under the Special Manpower Development Program (SMDP) of the Ministry of Electronics and Information Technology (MEITY), Government of India.

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Mopuri, S., Acharyya, A. Configurable Rotation Matrix of Hyperbolic CORDIC for Any Logarithm and Its Inverse computation. Circuits Syst Signal Process 39, 2551–2573 (2020). https://doi.org/10.1007/s00034-019-01277-w

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