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An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2r Algorithm

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Abstract

In ultra-high sampling rates, FFT is widely used for acoustic emission signals. In this manuscript, the effectual architecture of hardware is presented based on the execution of FFT due to radix-2 frequency decimation algorithm (R2DIF) and channeled method that allows data to be effectively shared through storage by shift registers. An optimal rotation method/design uses the modified digital coordinate rotation computer algorithm (m-CORDIC) as well as Radix- 2r depending on coding scheme to replace complex multiplier as FFT. The m-CORDIC algorithm enhances computing confluence, while Radix-2r allows the logarithmic reduction of the adder steps. The suggested design does not need large blocks of memory used to maintain the factor as twiddle. Experimental outcomes displays the presented design performs the existing methods by achieving high accuracy and throughput. Compared to the CSD as well as DBNS, novel radix-2r encoding desires an average of 23.12% and 3.07% fewer additions, respectively. The expansion of CSD is canonical signed-digit.

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, R.M.K Engineering College, Thiruvallur district, Tamil Nadu, India

    M. S. Kavitha

  2. Department of Electrical and Electronics Engineering, R.M.D. Engineering College, Kavaraipettai, Tamil Nadu, India

    P. Rangarajan

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  1. M. S. Kavitha
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Kavitha, M.S., Rangarajan, P. An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2r Algorithm. Circuits Syst Signal Process 39, 5801–5829 (2020). https://doi.org/10.1007/s00034-020-01436-4

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